ZHCSX71 October 2024 ADC3908D025 , ADC3908D065 , ADC3908D125 , ADC3908S025 , ADC3908S065 , ADC3908S125
PRODUCTION DATA
| 参数 | 测试条件 | 最小值 | 标称值 | 最大值 | 单位 | |
|---|---|---|---|---|---|---|
| ADC 时序规格 | ||||||
| tAD | 孔径延迟 | 0.5 | ns | |||
| tA | 孔径抖动 | 具有快速边缘的方波时钟 | 250 | fs | ||
| tACQ | 信号采集周期，以采样时钟下降沿为基准 | -TS/5 |
采样时钟周期 | |||
| tCONV | 信号转换周期，以采样时钟下降沿为基准 | Fs = 25MSPS | 5.5 | ns | ||
| Fs = 65MSPS | 5.5 | ns | ||||
| Fs = 125MSPS | 5.5 | ns | ||||
| 唤醒时间 | 断电后的数据有效时间。内部基准。 | 30 | us | |||
| ADC 延迟 | 信号输入到数据输出 | DDR | 1 | ADC 时钟周期 | ||
| SDR | 1 | |||||
| 接口时序 - DDR CMOS | ||||||
| tPD | 传播延迟：采样时钟下降沿到 DCLK 上升沿 | TS/4 + 3 | ns | |||
| tDE | DCLK 边沿到上一个数据转换 | Fs = 25MSPS | -10 | -9 | ns | |
| Fs = 65MSPS | -3.8 | -3.4 | ||||
| Fs = 125MSPS | -2 | -1.8 | ||||
| tDL | DCLK 边沿到下一个数据转换 | Fs = 25MSPS | 9 | 10 | ||
| Fs = 65MSPS | 3.4 | 3.8 | ||||
| Fs = 125MSPS | 1.8 | 2 | ||||
| 接口时序 - SDR CMOS | ||||||
| tPD | 传播延迟：采样时钟下降沿到 DCLK 上升沿 | TS/4 + 3 | ns | |||
| tDE | DCLK 边沿到上一个数据转换 | Fs = 25MSPS | -20 | -18 | ns | |
| Fs = 65MSPS | -7.6 | -6.9 | ||||
| Fs = 125MSPS | -4 | -3.6 | ||||
| tDV | DCLK 边沿到下一个数据转换 | Fs = 25MSPS | 18 | 20 | ||
| Fs = 65MSPS | 6.9 | 7.7 | ||||
| Fs = 125MSPS | 3.6 | 4 | ||||