ZHCSSA6C september 2009 – june 2023 ADS1000-Q1
PRODUCTION DATA
| PARAMETER | FAST MODE | HIGH-SPEED MODE | UNIT | |||
|---|---|---|---|---|---|---|
| MIN | MAX | MIN | MAX | |||
| f(SCL) | SCL operating frequency | 0.4 | 3.4 | MHz | ||
| t(BUF) | Bus free time between STOP and START conditions | 600 | 160 | ns | ||
| t(HDSTA) | Hold time after repeated START
condition. After this period, the first clock is generated. |
600 | 160 | ns | ||
| t(SUSTA) | Repeated START condition setup time | 600 | 160 | ns | ||
| t(SUSTO) | STOP condition setup time | 600 | 160 | ns | ||
| t(HDDAT) | Data hold time | 0 | 0 | ns | ||
| t(SUDAT) | Data setup time | 100 | 10 | ns | ||
| t(LOW) | SCL low period | 1300 | 160 | ns | ||
| t(HIGH) | SCL high period | 600 | 60 | ns | ||
| tF | Clock, data fall time | 300 | 160 | ns | ||
| tR | Clock, data rise time | 300 | 160 | ns | ||