ZHCSSA6C september 2009 – june 2023 ADS1000-Q1
PRODUCTION DATA
A user controls the ADS1000-Q1 operating mode and PGA settings through the 8-bit configuration register. The configuration register format is shown in Figure 7-2. The default setting is 80h.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
ST/BSY | Reserved | SC | Reserved | PGA[1:0] |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | ST/BSY | RW | 1b |
The meaning of the ST/BSY bit depends on whether the bit is being written to or read from. In single conversion mode, writing a 1b to the ST/BSY bit causes a conversion to start, and writing a 0b has no effect. In continuous conversion mode, the ADS1000-Q1 ignores the value written to ST/BSY. When read in single conversion mode, ST/BSY indicates whether the A/D converter is busy taking a conversion. If ST/BSY is read as 1b, the A/D converter is busy, and a conversion is taking place; if 0b, no conversion is taking place, and the result of the last conversion is available in the output register. In continuous conversion mode, ST/BSY is always read as 1b. |
6-5 | Reserved | R | 00b | Reserved. Always reads 00b. |
4 | SC | RW | 0b | SC controls whether the ADS1000-Q1 is in
continuous conversion or single conversion mode. 0b: Continuous conversion mode 1b: Single conversion mode |
3-2 | Reserved | R | 00b | Reserved. Always reads 00b. |
1-0 | PGA[1:0] | RW | 00b | PGA[1:0] bits control the ADS1000-Q1 gain setting. 00b: Gain = 1 01b: Gain = 2 10b: Gain = 4 11b: Gain = 8 |