ZHCSHA6E May 2009 – January 2018 ADS1013 , ADS1014 , ADS1015
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagrams
- 8.3 Feature Description
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6 Register Map
-
9 Application and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Shunt Resistor Considerations
- 9.2.2.2 Operational Amplifier Considerations
- 9.2.2.3 ADC Input Common-Mode Considerations
- 9.2.2.4 Resistor (R1, R2, R3, R4) Considerations
- 9.2.2.5 Noise and Input Impedance Considerations
- 9.2.2.6 First-order RC Filter Considerations
- 9.2.2.7 Circuit Implementation
- 9.2.2.8 Results Summary
- 9.2.3 Application Curves
- 10Power Supply Recommendations
- 11Layout
- 12器件和文档支持
- 13机械、封装和可订购信息
8.3.2 Analog Inputs
The ADS101x use a switched-capacitor input stage where capacitors are continuously charged and then discharged to measure the voltage between AINP and AINN. The frequency at which the input signal is sampled is called the sampling frequency or the modulator frequency (fMOD). The ADS101x has a 1-MHz internal oscillator that is further divided by a factor of 4 to generate fMOD at 250 kHz. The capacitors used in this input stage are small, and to external circuitry, the average loading appears resistive. Figure 11 shows this structure. The capacitor values set the resistance and switching rate. Figure 12 shows the timing for the switches in Figure 11. During the sampling phase, switches S1 are closed. This event charges CA1 to V(AINP), CA2 to V(AINN), and CB to (V(AINP) – V(AINN)). During the discharge phase, S1 is first opened and then S2 is closed. Both CA1 and CA2 then discharge to approximately 0.7 V and CB discharges to 0 V. This charging draws a very small transient current from the source driving the ADS101x analog inputs. The average value of this current can be used to calculate the effective impedance (Zeff), where Zeff = VIN / IAVERAGE.
Figure 11. Simplified Analog Input Circuit
Figure 12. S1 and S2 Switch TimingThe common-mode input impedance is measured by applying a common-mode signal to the shorted AINP and AINN inputs and measuring the average current consumed by each pin. The common-mode input impedance changes depending on the full-scale range, but is approximately 6 MΩ for the default full-scale range. In Figure 11, the common-mode input impedance is ZCM.
The differential input impedance is measured by applying a differential signal to AINP and AINN inputs where one input is held at 0.7 V. The current that flows through the pin connected to 0.7 V is the differential current and scales with the full-scale range. In Figure 11, the differential input impedance is ZDIFF.
Make sure to consider the typical value of the input impedance. Unless the input source has a low impedance, the ADS101x input impedance may affect the measurement accuracy. For sources with high-output impedance, buffering may be necessary. Active buffers introduce noise, and also introduce offset and gain errors. Consider all of these factors in high-accuracy applications.
The clock oscillator frequency drifts slightly with temperature; therefore, the input impedances also drift. For most applications, this input impedance drift is negligible, and can be ignored.