ZHCSEB2A October 2015 – November 2015 ADS1018-Q1
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Power-supply voltage | VDD to GND | –0.3 | 5.5 | V |
Analog input voltage | AIN0, AIN1, AIN2, AIN3 | GND – 0.3 | VDD + 0.3 | V |
Digital input voltage | DIN, DOUT/DRDY, SCLK, CS | GND – 0.3 | VDD + 0.3 | V |
Input current, continuous | Any pin except power supply pins | –10 | 10 | mA |
Temperature | Junction, TJ | –40 | 150 | °C |
Storage, Tstg | –60 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) | ±2000 | V |
Charged device model (CDM), per AEC Q100-011 | ±1000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
POWER SUPPLY | ||||||
VDD | Power supply | VDD to GND | 2 | 5.5 | V | |
ANALOG INPUTS(2) | ||||||
FSR | Full-scale input voltage(1) | VIN = V(AINP) - V(AINN) | See Table 1 | |||
V(AINx) | Absolute input voltage | GND | VDD | V | ||
DIGITAL INPUTS | ||||||
Input voltage | GND | VDD | V | |||
TEMPERATURE | ||||||
TA | Operating ambient temperature | –40 | 125 | °C |
THERMAL METRIC(1) | ADS1018-Q1 | UNIT | |
---|---|---|---|
DGS (VSSOP) | |||
10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 186.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 51.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 108.4 | °C/W |
ψJT | Junction-to-top characterization parameter | 2.7 | °C/W |
ψJB | Junction-to-board characterization parameter | 106.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUTS | ||||||
Common-mode input impedance | FSR = ±6.144 V(1) | 8 | MΩ | |||
FSR = ±4.096 V(1), FSR = ±2.048 V | 6 | |||||
FSR = ±1.024 V | 3 | |||||
FSR = ±0.512 V, FSR = ±0.256 V | 100 | |||||
Differential input impedance | FSR = ±6.144 V(1) | 22 | MΩ | |||
FSR = ±4.096 V(1) | 15 | |||||
FSR = ±2.048 V | 4.9 | |||||
FSR = ±1.024 V | 2.4 | |||||
FSR = ±0.512 V, FSR = ±0.256 V | 710 | kΩ | ||||
SYSTEM PERFORMANCE | ||||||
Resolution (no missing codes) | 12 | Bits | ||||
DR | Data rate | 128, 250, 490, 920, 1600, 2400, 3300 | SPS | |||
Data rate variation | All data rates | –10% | 10% | |||
INL | Integral nonlinearity | DR = 128 SPS, FSR = ±2.048 V(1) | 0.5 | LSB | ||
Offset error | FSR = ±2.048 V, differential inputs | 0 | ±0.5 | LSB | ||
FSR = ±2.048 V, single-ended inputs | ±0.25 | |||||
Offset drift | FSR = ±2.048 V | 0.002 | LSB/°C | |||
Offset channel match | Match between any two inputs | 0.25 | LSB | |||
Gain error(2) | FSR = ±2.048 V, TA = 25°C | 0.05% | 0.25% | |||
Gain drift(2)(3) | FSR = ±0.256 V | 7 | ppm/°C | |||
FSR = ±2.048 V | 5 | 40 | ||||
FSR = ±6.144 V(1) | 5 | |||||
Gain match(2) | Match between any two gains | 0.02% | 0.1% | |||
Gain channel match | Match between any two inputs | 0.05% | 0.1% | |||
TEMPERATURE SENSOR | ||||||
Temperature range | –40 | 125 | °C | |||
Temperature resolution | 0.125 | °C/LSB | ||||
Accuracy | TA = 0°C to 70°C | 0.25 | ±1 | °C | ||
TA = –40°C to +125°C | 0.5 | ±2 | ||||
vs supply | 0.125 | ±1 | °C/V | |||
DIGITAL INPUTS/OUTPUTS | ||||||
VIH | High-level input voltage | 0.7 VDD | VDD | V | ||
VIL | Low-level input voltage | GND | 0.2 VDD | V | ||
VOH | High-level output voltage | IOH = 1 mA | 0.8 VDD | V | ||
VOL | Low-level output voltage | IOL = 1 mA | GND | 0.2 VDD | V | |
IH | Input leakage, high | VIH = 5.5 V | –10 | 10 | μA | |
IL | Input leakage, low | VIL = GND | –10 | 10 | μA | |
POWER SUPPLY | ||||||
IVDD | Supply current | Power-down, TA = 25°C | 0.5 | 2 | μA | |
Power-down | 5 | |||||
Operating, TA = 25°C | 150 | 200 | ||||
Operating | 300 | |||||
PD | Power dissipation | VDD = 5 V | 0.9 | mW | ||
VDD = 3.3 V | 0.5 | |||||
VDD = 2 V | 0.3 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
tCSSC | Delay time, CS falling edge to first SCLK rising edge(1) | 100 | ns | |
tSCCS | Delay time, final SCLK falling edge to CS rising edge | 100 | ns | |
tCSH | Pulse duration, CS high | 200 | ns | |
tSCLK | SCLK period | 250 | ns | |
tSPWH | Pulse duration, SCLK high | 100 | ns | |
tSPWL | Pulse duration, SCLK low(2) | 100 | ns | |
28 | ms | |||
tDIST | Setup time, DIN valid before SCLK falling edge | 50 | ns | |
tDIHD | Hold time, DIN valid after SCLK falling edge | 50 | ns | |
tDOHD | Hold time, SCLK rising edge to DOUT invalid | 0 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tCSDOD | Propagation delay time, CS falling edge to DOUT driven |
DOUT load = 20 pF || 100 kΩ to GND | 100 | ns | ||
tDOPD | Propagation delay time, SCLK rising edge to valid new DOUT |
DOUT load = 20 pF || 100 kΩ to GND | 0 | 50 | ns | |
tCSDOZ | Propagation delay time, CS rising edge to DOUT high impedance |
DOUT load = 20 pF || 100 kΩ to GND | 100 | ns |