米6体育平台手机版

ZHCSE76E December 2011 – December 2022 ADS1113-Q1 , ADS1114-Q1 , ADS1115-Q1

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

DGS|10
- MPDS035C
NKS|10
- MPQF680

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.5 Electrical Characteristics

at VDD = 3.3 V, data rate = 8 SPS, and full-scale input voltage range (FSR) = ±2.048 V (unless otherwise noted); maximum and minimum specifications apply from T_A = –40°C to +125°C; typical specifications are at T_A = 25°C

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
ANALOG INPUT
	Common-mode input impedance	FSR = ±6.144 V⁽¹⁾			10		MΩ
		FSR = ±4.096 V⁽¹⁾, FSR = ±2.048 V			6
		FSR = ±1.024 V			3
		FSR = ±0.512 V, FSR = ±0.256 V			100		kΩ
	Differential input impedance	FSR = ±6.144 V⁽¹⁾			22		MΩ
		FSR = ±4.096 V⁽¹⁾			15
		FSR = ±2.048 V			4.9
		FSR = ±1.024 V			2.4
		FSR = ±0.512 V, ±0.256 V			710		kΩ
SYSTEM PERFORMANCE
	Resolution (no missing codes)			16			Bits
DR	Data rate			8, 16, 32, 64, 128, 250, 475, 860			SPS
	Data rate variation	All data rates		–10%		10%
	Output noise			See Section 7.1 section
INL	Integral nonlinearity	DR = 8 SPS, FSR = ±2.048 V⁽²⁾				1	LSB
	Offset error	FSR = ±2.048 V, differential inputs		–3	±1	3	LSB
	Offset error	FSR = ±2.048 V, single-ended inputs			±3		LSB
	Offset drift over temperature	FSR = ±2.048 V			0.005		LSB/°C
	Long-term Offset drift	FSR = ±2.048 V, T_A = 125°C, 1000 hrs			±1		LSB
	Offset power-supply rejection	FSR = ±2.048 V, DC supply variation			1		LSB/V
	Offset channel match	Match between any two inputs			3		LSB
	Gain error⁽³⁾	FSR = ±2.048 V, T_A = 25°C			0.01%	0.15%
	Gain drift over temperature⁽³⁾	FSR = ±0.256 V			7		ppm/°C
		FSR = ±2.048 V			5	40
		FSR = ±6.144 V⁽¹⁾			5
	Long-term gain drift⁽³⁾	FSR = ±2.048 V, T_A = 125°C, 1000 hrs			±0.05		%
	Gain power-supply rejection				80		ppm/V
	Gain match⁽³⁾	Match between any two gains			0.02%	0.1%
	Gain channel match	Match between any two inputs			0.05%	0.1%
CMRR	Common-mode rejection ratio	At DC, FSR = ±0.256 V			105		dB
		At DC, FSR = ±2.048 V			100
		At DC, FSR = ±6.144 V⁽¹⁾			90
		f_CM = 60 Hz, DR = 8 SPS			105
		f_CM = 50 Hz, DR = 8 SPS			105
DIGITAL INPUT/OUTPUT
V_IH	High-level input voltage			0.7 VDD		5.5	V
V_IL	Low-level input voltage			GND		0.3 VDD	V
V_OL	Low-level output voltage	I_OL = 3 mA		GND	0.15	0.4	V
	Input leakage current	GND < V_DIG < VDD		–10		10	µA
POWER-SUPPLY
I_VDD	Supply current	Power-down	T_A = 25°C		0.5	2	µA
		Power-down				5
		Operating	T_A = 25°C		150	200
		Operating				300
P_D	Power dissipation	VDD = 5.0 V			0.9		mW
		VDD = 3.3 V			0.5
		VDD = 2.0 V			0.3

(1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V must be applied to the analog inputs of the device. See Table 8-1 for more information.

(2) Best-fit INL; covers 99% of full-scale.

(3) Includes all errors from onboard PGA and voltage reference.