9.3.1 Multiplexer

The ADS1118-Q1 contains an input multiplexer (mux), as shown in Figure 29. Either four single-ended or two differential signals can be measured. Additionally, AIN0, AIN1, and AIN2 can be measured differentially to AIN3. The multiplexer is configured by bits MUX[2:0] in the Config register. When single-ended signals are measured, the negative input of the ADC is internally connected to GND by a switch within the multiplexer.

Figure 29. Input Multiplexer

When measuring single-ended inputs, the device does not output negative codes. These negative codes indicate negative differential signals; that is, (V_(AINP) – V_(AINN)) < 0. Electrostatic discharge (ESD) diodes to VDD and GND protect the ADS1118-Q1 inputs. To prevent the ESD diodes from turning on, keep the absolute voltage on any input within the range given in Equation 3:

If the voltages on the input pins can possibly violate these conditions, use external Schottky diodes and series resistors to limit the input current to safe values (see the Absolute Maximum Ratings table).

Also, overdriving one unused input on the ADS1118-Q1 may affect conversions currently taking place on other input pins. If overdriving unused inputs is possible, clamp the signal with external Schottky diodes.

9.3.2 Analog Inputs

The ADS1118-Q1 uses a switched-capacitor input stage where capacitors are continuously charged and then discharged to measure the voltage between AIN_P and AIN_N. This frequency at which the input signal is sampled is called the sampling frequency or the modulator frequency (f_(MOD)). The ADS1118-Q1 has a 1 MHz internal oscillator which is further divided by a factor of 4 to generate the modulator frequency at 250 kHz. The capacitors used in this input stage are small, and to external circuitry, the average loading appears resistive. This structure is shown in Figure 30. The resistance is set by the capacitor values and the rate at which they are switched. Figure 31 shows the setting of the switches illustrated in Figure 30. During the sampling phase, switches S₁ are closed. This event charges C_A1 to V_(AINP), C_A2 to V_(AINN), and C_B to (V_(AINP) – V_(AINN)). During the discharge phase, S₁ is first opened and then S₂ is closed. Both C_A1 and C_A2 then discharge to approximately 0.7 V and C_B discharges to 0 V. This charging draws a very small transient current from the source driving the ADS1118-Q1 analog inputs. The average value of this current can be used to calculate the effective impedance (Z_eff), where Z_eff = V_IN / I_AVERAGE.

Figure 30. Simplified Analog Input Circuit

Figure 31. S₁ and S₂ Switch Timing

Common-mode input impedance is measured by applying a common-mode signal to the shorted AIN_P and AIN_N inputs and measuring the average current consumed by each pin. The common-mode input impedance changes depending on the full-scale range, but is approximately 6 MΩ for the default full-scale range. In Figure 30, the common-mode input impedance is Z_CM.

The differential input impedance is measured by applying a differential signal to AIN_P and AIN_N inputs where one input is held at 0.7 V. The current that flows through the pin connected to 0.7 V is the differential current and scales with the full-scale range. In Figure 30, the differential input impedance is Z_DIFF.

Make sure to consider the typical value of the input impedance. Unless the input source has a low impedance, the ADS1118-Q1 input impedance may affect the measurement accuracy. For sources with high output impedance, buffering may be necessary. Active buffers introduce noise, and also introduce offset and gain errors. Consider all of these factors in high-accuracy applications.

The clock oscillator frequency drifts slightly with temperature; therefore, the input impedances also drift. For most applications, this input impedance drift is negligible, and can be ignored.

9.3.3 Full-Scale Range (FSR) and LSB Size

A programmable gain amplifier (PGA) is implemented in front of the ADS1118-Q1 ΔΣ ADC core. The full-scale range is configured by bits PGA[2:0] in the Config register, and can be set to ±6.144 V, ±4.096 V, ±2.048 V, ±1.024 V, ±0.512 V, or ±0.256 V.

Table 3 shows the FSR together with the corresponding LSB size. Calculate the LSB size from the full-scale voltage by the formula shown in Equation 4. However, make sure that the analog input voltage never exceeds the analog input voltage range limit given in the Electrical Characteristics. If VDD greater than 4 V is used, the ±6.144-V full-scale range allows input voltages to extend up to the supply. Note though that in this case, or whenever the supply voltage is less than the full-scale range (for example, VDD = 3.3 V and full-scale range = ±4.096 V), a full-scale ADC output code cannot be obtained. This inability means that some dynamic range is lost.

9.3.4 Voltage Reference

The ADS1118-Q1 has an integrated voltage reference. An external reference cannot be used with this device. Errors associated with the initial voltage reference accuracy and the reference drift with temperature are included in the gain error and gain drift specifications in the Electrical Characteristics.

9.3.5 Oscillator

The ADS1118-Q1 has an integrated oscillator running at 1 MHz. No external clock is required to operate the device. Note that the internal oscillator drifts over temperature and time. The output data rate scales proportionally with the oscillator frequency.

9.3.6 Temperature Sensor

The ADS1118-Q1 offers an integrated precision temperature sensor. To enable the temperature sensor mode, set bit TS_MODE = 1 in the Config register. Temperature data are represented as a 14-bit result that is left-justified within the 16-bit conversion result. Data are output starting with the most significant byte (MSB). When reading the two data bytes, the first 14 bits are used to indicate the temperature measurement result. One 14-bit LSB equals 0.03125°C. Negative numbers are represented in binary twos complement format, as shown in Table 4.

9.4.1 Reset and Power-Up

When the ADS1118-Q1 powers up, the device resets. As part of the reset process, the ADS1118-Q1 sets all bits in the Config register to the respective default settings. By default, the ADS1118-Q1 enters a power-down state at start-up. The device interface and digital blocks are active, but no data conversions are performed. The initial power-down state of the ADS1118-Q1 relieves systems with tight power-supply requirements from encountering a surge during power-up.

9.4.2 Operating Modes

The ADS1118-Q1 operates in one of two modes: continuous-conversion or single-shot. The MODE bit in the Config register selects the respective operating mode.

9.4.3 Duty Cycling for Low Power

The noise performance of a ΔΣ ADC generally improves when lowering the output data rate because more samples of the internal modulator are averaged to yield one conversion result. In applications where power consumption is critical, the improved noise performance at low data rates may not be required. For these applications, the ADS1118-Q1 supports duty cycling that can yield significant power savings by periodically requesting high data-rate readings at an effectively lower data rate.

For example, an ADS1118-Q1 in power-down state with a data rate set to 860 SPS can be operated by a microcontroller that instructs a single-shot conversion every 125 ms (8 SPS). A conversion at 860 SPS only requires approximately 1.2 ms; therefore, the ADS1118-Q1 enters power-down state for the remaining 123.8 ms. In this configuration, the ADS1118-Q1 consumes approximately 1/100th the power that is otherwise consumed in continuous-conversion mode. The duty cycling rate is completely arbitrary and is defined by the master controller. The ADS1118-Q1 offers lower data rates that do not implement duty cycling and also offers improved noise performance, if required.

9.5.1 Serial Interface

The SPI-compatible serial interface consists of either four signals (CS, SCLK, DIN, and DOUT/DRDY), or three signals (SCLK, DIN, and DOUT/DRDY, with CS tied low). The interface is used to read conversion data, read from and write to registers, and control device operation.

9.5.2 Chip Select (CS)

The chip select pin (CS) selects the ADS1118-Q1 for SPI communication. This feature is useful when multiple devices share the same serial bus. Keep CS low for the duration of the serial communication. When CS is taken high, the serial interface is reset, SCLK is ignored, and DOUT/DRDY enters a high-impedance state. In this state, DOUT/DRDY cannot provide data-ready indication. In situations where multiple devices are present and DOUT/DRDY must be monitored, lower CS periodically. At this point, the DOUT/DRDY pin either immediately goes high to indicate that no new data are available, or immediately goes low to indicate that new data are present in the Conversion register and are available for transfer. New data can be transferred at any time without concern of data corruption. When a transmission starts, the current result is locked into the output shift register and does not change until the communication completes. This system avoids any possibility of data corruption.

9.5.3 Serial Clock (SCLK)

The serial clock pin (SCLK) features a Schmitt-triggered input and is used to clock data on the DIN and DOUT/DRDY pins into and out of the ADS1118-Q1. Even though the input has hysteresis, keep SCLK as clean as possible to prevent glitches from accidentally shifting the data. To reset the serial interface, hold SCLK low for 28 ms, and the next SCLK pulse starts a new communication cycle. Use this time-out feature to recover communication when a serial interface transmission is interrupted. When the serial interface is idle, hold SCLK low.

9.5.4 Data Input (DIN)

The data input pin (DIN) is used along with SCLK to send data to the ADS1118-Q1. The device latches data on DIN at the SCLK falling edge. The ADS1118-Q1 never drives the DIN pin.

9.5.5 Data Output and Data Ready (DOUT/DRDY)

The data output and data ready pin (DOUT/DRDY) is used with SCLK to read conversion and register data from the ADS1118-Q1. Data on DOUT/DRDY are shifted out on the SCLK rising edge. DOUT/DRDY is also used to indicate that a conversion is complete and new data are available. This pin transitions low when new data are ready for retrieval. DOUT/DRDY is also able to trigger a microcontroller to start reading data from the ADS1118-Q1. In continuous-conversion mode, DOUT/DRDY transitions high again 8 µs before the next data ready signal (DOUT/DRDY low) if no data are retrieved from the device. This transition is shown in Figure 32. Complete the data transfer before DOUT/DRDY returns high.

1.

NOINDENT:

CS can be held low if the ADS1118-Q1 does not share the serial bus with another device. If CS is low, DOUT/DRDY asserts low indicating new data are available.

Figure 32. DOUT/DRDY Behavior Without Data Retrieval in Continuous-Conversion Mode

When CS is high, DOUT/DRDY is configured by default with a weak internal pullup resistor. This feature reduces the risk of DOUT/DRDY floating near midsupply and causing leakage current in the master device. To disable this pullup resistor and place the device into a high-impedance state, set the PULL_UP_EN bit to 0 in the Config register.

9.5.6 Data Format

The ADS1118-Q1 provides 16 bits of data in binary twos complement format. A positive full-scale (+FS) input produces an output code of 7FFFh and a negative full-scale (–FS) input produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale. Table 5 summarizes the ideal output codes for different input signals. Figure 33 shows code transitions versus input voltage.

Figure 33. Code Transition Diagram

9.5.7 Data Retrieval

Data is written to and read from the ADS1118-Q1 in the same manner for both single-shot and continuous conversion modes, without having to issue any commands. The operating mode for the ADS1118-Q1 is selected by the MODE bit in the Config register.

Set the MODE bit to 0 to put the device in continuous-conversion mode. In continuous-conversion mode, the device is constantly starting new conversions even when CS is high.

Set the MODE bit to 1 for single-shot mode. In single-shot mode, a new conversion only starts by writing a 1 to the SS bit.

The conversion data are always buffered, and retain the current data until replaced by new conversion data. Therefore, data can be read at any time without concern of data corruption. When DOUT/DRDY asserts low, indicating that new conversion data are ready, the conversion data are read by shifting the data out on DOUT/DRDY. The MSB of the data (bit 15) on DOUT/DRDY is clocked out on the first SCLK rising edge. At the same time that the conversion result is clocked out of DOUT/DRDY, new Config register data are latched on DIN on the SCLK falling edge.

The ADS1118-Q1 also offers the possibility of direct readback of the Config register settings in the same data transmission cycle. One complete data transmission cycle consists of either 32 bits (when the Config register data readback is used) or 16 bits (only used when the CS line can be controlled and is not permanently tied low).

9.5.7.1 32-Bit Data Transmission Cycle

The data in a 32-bit data transmission cycle consist of four bytes: two bytes for the conversion result, and an additional two bytes for the Config register readback. The device always reads the MSB first.

Write the same Config register setting twice during one transmission cycle as shown in Figure 34. If convenient, write the Config register setting once during the first half of the transmission cycle, and then hold the DIN pin either low (as shown in Figure 35) or high during the second half of the cycle. If no update to the Config register is required, hold the DIN pin either low or high during the entire transmission cycle. The Config register setting written in the first two bytes of a 32-bit transmission cycle is read back in the last two bytes of the same cycle.

1.

NOINDENT:

CS can be held low if the ADS1118-Q1 does not share the serial bus with another device. If CS is low, DOUT/DRDY asserts low indicating new data are available.

Figure 34. 32-Bit Data Transmission Cycle With Config Register Readback

1.

NOINDENT:

CS can be held low if the ADS1118-Q1 does not share the serial bus with another device. If CS is low, DOUT/DRDY asserts low indicating new data are available.

Figure 35. 32-Bit Data Transmission Cycle: DIN Held Low

Figure 36. 16-Bit Data Transmission Cycle

9.6.1 Conversion Register [reset = 0000h]

The 16-bit Conversion register contains the result of the last conversion in binary twos complement format. Following power up, the Conversion register is cleared to 0, and remains 0 until the first conversion is complete. The register format is shown in Figure 37.

9.6.2 Config Register [reset= 058Bh]

The 16-bit Config register can be used to control the ADS1118-Q1 operating mode, input selection, data rate, full-scale range, and temperature sensor mode. The register format is shown in Figure 38.