The device requires a single power supply, VDD, to power both the analog and digital circuitry of the device.

11.1 Power-Supply Sequencing

Wait approximately 50 µs after VDD is stabilized before communicating with the device to allow the power-up reset process to complete.

11.2 Power-Supply Decoupling

Good power-supply decoupling is important to achieve optimum performance. VDD must be decoupled with at least a 0.1-µF capacitor, as shown in Figure 48. The 0.1-μF bypass capacitor supplies the momentary bursts of extra current required from the supply when the ADS1118-Q1 is converting. Place the bypass capacitor as close to the power-supply pin of the device as possible using low-impedance connections. For best performance, use multilayer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes.

Figure 48. Power Supply Decoupling