Table 29. 3-Wire RTD Application Requirements

9.2.1.2.1 Topology

Figure 69 shows the basic topology of a ratiometric measurement using an RTD. Shown are the ADC with the RTD and a reference resistor R_REF. A single current source, labeled IDAC1, is used to excite the RTD as well as to establish a reference voltage for the ADC across R_REF.

Figure 69. Example of a Ratiometric RTD Measurement

With IDAC1, the ADC measures the RTD voltage using the voltage across R_REF as the reference. This process gives a measurement such that the output code is proportional to the ratio of the RTD voltage and the reference voltage, as shown in Equation 21 and Equation 22.

The currents cancel so that Equation 22 reduces to Equation 23:

As shown in Equation 23, the measurement depends on the resistive value of the RTD and the reference resistor R_REF, but not on the IDAC1 current value. Therefore, the absolute accuracy and temperature drift of the excitation current does not matter. This measurement is ratiometric. As long as there is no current leakage from IDAC1 outside of this circuit, the measurement depends only on R_RTD and R_REF.

In Figure 70, the lead resistances of a 3-wire RTD are shown and another excitation current source is added, labeled IDAC2.

Figure 70. Example of a Lead Wire Compensation

With a single excitation current source, R_LEAD1 adds an error to the measurement. By adding IDAC2, the second excitation current source is used to cancel out the error in the lead wire resistance. When adding the lead resistances and the second current source, Equation 22 becomes:

If the lead resistances match and the excitation currents match, then R_LEAD1 = R_LEAD2 and I_IDAC1 = I_IDAC2. The lead wire resistances cancel out so that Equation 24 reduces to the result in Equation 25, thus maintaining a ratiometric measurement.

R_LEAD3 is not part of the measurement because this lead resistance is not in the input measurement path or in the reference input path.

As Equation 24 shows, the two current sources must be matched to cancel the lead resistances of the RTD wires. Any mismatch in the two current sources is minimized by using the multiplexer to swap or chop the two current sources between the two inputs. Taking measurements in both configurations and averaging the readings reduces the effects of mismatched current sources. The design uses the multiplexer in the ADS1148-Q1 to implement this chopping technique to remove the mismatch error between IDAC1 and IDAC2.

9.2.1.2.2 RTD Selection

The RTD is first chosen to be a PT100 element. The RTD resistance is defined by the Callendar-Van Dusen (CVD) equations and the resistance of the RTD is known depending on the temperature. The PT100 RTD has an impedance of 100 Ω at 0˚C and roughly 0.385 Ω of resistance change per 1˚C in temperature change. With a desired temperature measurement accuracy of 0.2˚C, this value translates to a resistive measurement accuracy of approximately 0.077 Ω. The RTD resistance at the low end of the temperature range of –200˚C is 18.59 Ω and the resistance at the high end of the temperature range of 850˚C is 390.48 Ω.

9.2.1.2.3 Excitation Current

For the best possible resolution, the voltage across the RTD must be made as large as possible compared to the noise floor in the measurement. In general, measurement resolution improves with increasing excitation current. However, a larger excitation current creates self-heating in the RTD that causes drift and error in the measurement. The selection of excitation currents trades off resolution against sensor self-heating.

The excitation current sources in this design are selected to be 1 mA. This selection maximizes the value of the RTD voltage and keeps the self-heating low. The typical range of RTD self-heating coefficients is 2.5 mW/°C for small, thin-film elements and 65 mW/°C for larger, wire-wound elements. With a 1-mA excitation at the maximum RTD resistance value, the power dissipation in the RTD is less than 0.4 mW and keeps the measurement errors resulting from self-heating to less than 0.01˚C.

As mentioned in the Topology section, chopping of the excitation current sources cancels mismatches between the IDACs. This technique is necessary for obtaining the best possible accuracy from the system. Mismatch between the excitation current sources is a large source of error if chopping is not implemented.

The internal reference voltage must be enabled when using the IDACs, even if an external ratiometric measurement is used for ADC conversions.

Table 30 shows the ADS1148-Q1 register settings for setting up the internal reference and the excitation current sources.

9.2.1.2.4 Reference Resistor (R_REF)

The common-mode voltage of the measurement is recommended to be set near mid-supply, which helps keep the input within the common-mode input range of the PGA.

The reference resistor is selected to be 820 Ω. The voltage across R_REF is calculated from Equation 26.

With AVDD = 3.3 V, Equation 26 shows that the input voltage is just below mid-supply.

The excitation current sources operate properly to a maximum IDAC compliance voltage. The current sources lose current regulation above this compliance voltage. In this example, the output voltage of the excitation current source is calculated from the sum of the voltages across the RTD and R_REF, as shown in Equation 27.

A compliance voltage of 3.3 V – 2.04 V = 1.26 V is sufficient for proper IDAC operation. See Figure 9 and Figure 10 in the Typical Characteristics section for details.

Because the voltage across R_REF sets the reference voltage for the ADC, the tolerance and temperature drift of R_REF directly affects the measurement gain. A resistor with a 0.01% maximum tolerance is selected for this measurement.

9.2.1.2.5 PGA Setting

Because the excitation current is small to reduce self-heating, the PGA in the ADS1148-Q1 is used to amplify the signal across the RTD to use the full-scale range of the ADC. Starting with the reference voltage, the ADC is able to measure a differential input signal range of ±1.64 V. The maximum allowable PGA gain setting is based on the reference voltage, the maximum RTD resistance, and the excitation current.

As mentioned previously, the resistance of the RTD is a maximum of 850°C. The voltage measured at this temperature is at maximum and is given by:

With a reference voltage of 1.64 V, the maximum gain for the PGA, without overranging the ADC, is shown in Equation 29.

Selecting a PGA gain of 4 gives a maximum measurement of 95% of the positive full-scale range. Table 31 shows the register settings to set the PGA gain as well as the inputs for the ADC.

9.2.1.2.6 Common-Mode Input Range

Now that the component values are selected, the common-mode input range must be verified to ensure that the ADC and PGA are not limited in operation. Start with the maximum input voltage, which gives the most restriction in the common-mode input range. At the maximum input voltage, the common-mode input voltage detected by the ADC is shown in Equation 30.

As mentioned in the Low-Noise PGA section, the common-mode input range is shown in Equation 3 and is applied to Equation 31.

After substituting in the appropriate values, the common-mode input range can be found in Equation 32 and Equation 33.

Because V_CM = 1.835 V is within the limits of Equation 33, the RTD measurement is within the input common-mode range of the ADC and PGA. At the RTD voltage minimum (V_{RTD MIN} = 18.59 mV), a similar calculation can be made to show that the input common-mode voltage is within the range as well.

9.2.1.2.7 Input and Reference Low-Pass Filters

The differential filters chosen for this application are designed to have a –3-dB corner frequency at least 10 times larger than the bandwidth of the ADC. The selected ADS1148-Q1 sampling rate of 20 SPS results in a –3-dB bandwidth of 14.8 Hz. The –3-dB filter corner frequency is set to be roughly 250 Hz at a mid-scale measurement resistance. For proper operation, the differential cutoff frequencies of the reference and input low-pass filters must be well matched. This matching can be difficult because when the resistance of the RTD changes over the span of the measurement, the filter cutoff frequency changes as well. To mitigate this effect, the two resistors used in the input filter (R_I1 and R_I2) are chosen to be two orders of magnitude larger than the RTD. Input bias currents of the ADC causes a voltage drop across the filter resistors that shows up as a differential offset error if the bias currents or filter resistors are not equal. The resistors are recommended to be limited to at most 10 kΩ to reduce dc offset errors resulting from the input bias current. R_I1 and R_I2 are chosen to be 4.7 kΩ.

The input filter differential capacitor (C_{I_DIFF}) is calculated starting from the cutoff frequency, as shown in Equation 34 and Equation 35.

After solving for C_{I_DIFF}, the capacitor is chosen to be a standard value of 68 nF.

To ensure that mismatch of the common-mode filter capacitors does not translate to a differential voltage, the common-mode capacitors (C_{I_CM1} and C_{I_CM2}) are chosen to be 10 times smaller than the differential capacitor, making each capacitor 6.8 nF. These capacitor values result in a common-mode cutoff frequency that is roughly 20 times larger than the differential filter, making the matching of the common-mode cutoff frequencies less critical.

After substituting values into Equation 36 and Equation 37, the common-mode cutoff frequencies are found to be f_{–3dB_CM+} = 4.13 kHz and f_{–3dB_CM–} = 4.24 kHz, respectively.

Often, filtering the reference input is not necessary and adding bulk capacitance at the reference input is sufficient. However, equations showing a design procedure calculating filter values for the reference inputs are shown in Equation 38 and Equation 39.

The differential reference filter is designed to have a –3-dB corner frequency of 250 Hz to match the differential input filter. The two reference filter resistors are selected to be 9.09 kΩ, which is several times larger than the value of R_REF. The reference filter resistors must not be sized larger than 10 kΩ or dc bias errors become significant. The differential capacitor for the reference filter is calculated as shown in Equation 38.

After solving for C_{R_DIFF}, the capacitor is chosen to be a standard value of 33 nF.

To ensure that mismatch of the common-mode filter capacitors does not translate to a differential voltage, the reference common-mode capacitors (C_{R_CM1} and C_{R_CM2}) are chosen to be 10 times smaller than the reference differential capacitor, making these capacitors each 3.3 nF. Again, the resulting cutoff frequency for the common-mode filters is roughly 20 times larger than the differential filter, making the matching of the cutoff frequencies less critical.

After substituting values into Equation 40 and Equation 41, common-mode cutoff frequencies for the reference filter are found to be f_{–3dB_CM+} = 4.87 kHz and f_{–3dB_CM+} = 5.31 kHz, respectively.

9.2.1.2.8 Register Settings

The register settings for this design are shown in Table 32.

Table 33. Comparison of Design Goals and Measured Performance

Table 34. Example Thermocouple Application Requirements

9.2.2.2.1 Biasing Resistors

The biasing resistors R_B1 and R_B2 are used to set the common-mode voltage of the thermocouple to within the specified common-mode voltage range of the PGA (in this example, to mid-supply AVDD / 2). If the application requires the thermocouple to be biased to GND, a bipolar supply (for example, AVDD = 2.5 V and AVSS = –2.5 V) must be used for the device to meet the common-mode voltage requirement of the PGA. When choosing the values of the biasing resistors, care must be taken so that the biasing current does not degrade measurement accuracy. The biasing current flows through the thermocouple and can cause self-heating and additional voltage drops across the thermocouple leads. Typical values for the biasing resistors range from 1 MΩ to 50 MΩ.

In addition to biasing the thermocouple, R_B1 and R_B2 are also useful for detecting an open thermocouple lead. When one of the thermocouple leads fails open, the biasing resistors pull the analog inputs (AIN0 and AIN1) to AVDD and AVSS, respectively. The ADC consequently reads a full-scale value, which is outside the normal measurement range of the thermocouple voltage, to indicate this failure condition.

9.2.2.2.2 Input Filtering

Although the digital filter attenuates high-frequency components of noise, a first-order, passive RC filter is recommended to be provided at the inputs to further improve performance. The differential RC filter formed by R_I1, R_I2, and the differential capacitor C_{I_DIFF} offers a cutoff frequency that is calculated using Equation 43.

Two common-mode filter capacitors (C_{I_CM1} and C_{I_CM2}) are also added to offer attenuation of high-frequency, common-mode noise components. The differential capacitor C_{I_DIFF} is recommended to be at least an order of magnitude (10 times) larger than the common-mode capacitors (C_{I_CM1} and C_{I_CM2}) because mismatches in the common-mode capacitors can convert common-mode noise into differential noise.

The filter resistors R_F1 and R_F2 also serve as current-limiting resistors. These resistors limit the current into the analog inputs (AIN0 and AIN1) of the device to safe levels if an overvoltage on the inputs occurs. Care must be taken when choosing the filter resistor values because the input currents flowing into and out of the device cause a voltage drop across the resistors. This voltage drop shows up as an additional offset error at the ADC inputs. For thermocouple measurements, limit the filter resistor values to below 10 kΩ.

The filter component values used in this design are: R_I1 = R_I2 = 1 kΩ, C_{I_DIFF} = 100 nF, and C_{I_CM1} = C_{I_CM2} = 10 nF.

9.2.2.2.3 PGA Setting

The highest measurement resolution is achieved when matching the largest potential input signal to the FSR of the ADC by choosing the highest possible gain. From the design requirement, the maximum thermocouple voltage occurs at T_TC = 1250°C and is V_TC = 50.644 mV, as defined in the tables published by the National Institute of Standards and Technology (NIST) using a cold-junction temperature of T_CJ = 0°C. A thermocouple produces an output voltage that is proportional to the temperature difference between the thermocouple tip and the cold junction. If the cold junction is at a temperature below 0°C, the thermocouple produces a voltage larger than 50.644 mV. The isothermal block area is constrained by the operating temperature range of the device. Therefore, the isothermal block temperature is limited to –40°C. A K-type thermocouple at T_TC = 1250°C produces an output voltage of V_TC = 50.644 mV – (–1.527 mV) = 52.171 mV when referenced to a cold-junction temperature of T_CJ = –40°C. The maximum gain that can be applied when using the internal 2.048-V reference is then calculated as 39.3 from Equation 44. The next smaller PGA gain setting the device offers is 32.

9.2.2.2.4 Cold-Junction Measurement

AIN2 and AIN3 are attached to a 3-wire RTD that is used to measure the cold-junction temperature. Similar to the example in the Ratiometric 3-Wire RTD Measurement System section, the 3-wire RTD design is the same except the inputs and excitation current sources have been changed. Note that R_REF and PGA Gain can be optimized for a reduced temperature range.

The device does not perform an automatic cold-junction compensation of the thermocouple. This compensation must be done in the microcontroller that interfaces to the device. The microcontroller requests one or multiple readings of the thermocouple voltage from the device and then sets the device to measure the cold junction with the RTD to compensate for the cold-junction temperature.

An algorithm similar to the following must be implemented on the microcontroller to compensate for the cold-junction temperature:

1. Measure the thermocouple voltage, V_(TC), between AIN0 and AIN1.
2. Measure the temperature of the cold junction, T_(CJ), using a ratiometric measurement with the 3-wire RTD across AIN2 and AIN3.
3. Convert the cold-junction temperature into an equivalent thermoelectric voltage, V_(CJ), using the tables or equations provided by NIST.
4. Add V_(TC) and V_(CJ) and translate the summation back into a thermocouple temperature using the NIST tables or equations again.

There are alternate methods of measuring the cold-junction temperature. The additional analog input channels of the device can be used in this case to measure the cold-junction temperature with a thermistor or an alternate analog temperature sensor.

9.2.2.2.5 Calculated Resolution

To get an approximation of the achievable temperature resolution, the peak-to-peak noise of the ADS1148-Q1 at gain = 32 and DR = 20 SPS (1.95 µV_PP) is taken from Table 1. The noise is divided by the average sensitivity of a K-type thermocouple (41 µV/°C), as shown in Equation 45.

9.2.2.2.6 Register Settings

The register settings for this design are shown in Table 35. The inputs are selected to measure the thermocouple and the internal reference is enabled and selected. The excitation current sources are also enabled and selected. Although this configuration consumes some power, this setting allows for a quick transition for the cold-junction measurement.

Changing to the cold-junction measurement, the registers are set to measure the RTD. This measurement requires changing the input, the reference input, the gain, and any calibration settings required for the measurement accuracy. Table 36 shows the register settings for the RTD measurement used for cold-junction compensation.