ZHCSFJ3A July   2014  – September 2016 ADS1148-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  ADC Input and Multiplexer
      2. 8.3.2  Low-Noise PGA
        1. 8.3.2.1 PGA Common-Mode Voltage Requirements
        2. 8.3.2.2 PGA Common-Mode Voltage Calculation Example
        3. 8.3.2.3 Analog Input Impedance
      3. 8.3.3  Clock Source
      4. 8.3.4  Modulator
      5. 8.3.5  Digital Filter
      6. 8.3.6  Voltage Reference Input
      7. 8.3.7  Internal Voltage Reference
      8. 8.3.8  Excitation Current Sources
      9. 8.3.9  Sensor Detection
      10. 8.3.10 Bias Voltage Generation
      11. 8.3.11 General-Purpose Digital I/O
      12. 8.3.12 System Monitor
        1. 8.3.12.1 Power-Supply Monitor
        2. 8.3.12.2 External Voltage Reference Monitor
        3. 8.3.12.3 Ambient Temperature Monitor
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Up
      2. 8.4.2 Reset
      3. 8.4.3 Power-Down Mode
      4. 8.4.4 Conversion Control
        1. 8.4.4.1 Settling Time for Channel Multiplexing
        2. 8.4.4.2 Channel Cycling and Overload Recovery
        3. 8.4.4.3 Single-Cycle Settling
        4. 8.4.4.4 Digital Filter Reset Operation
      5. 8.4.5 Calibration
        1. 8.4.5.1 Offset Calibration Register: OFC[2:0]
        2. 8.4.5.2 Full-Scale Calibration Register: FSC[2:0]
        3. 8.4.5.3 Calibration Commands
          1. 8.4.5.3.1 System Offset and Self Offset Calibration
          2. 8.4.5.3.2 System Gain Calibration
        4. 8.4.5.4 Calibration Timing
    5. 8.5 Programming
      1. 8.5.1 Digital Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Input (DIN)
        4. 8.5.1.4 Data Ready (DRDY)
        5. 8.5.1.5 Data Output and Data Ready (DOUT/DRDY)
        6. 8.5.1.6 SPI Reset
        7. 8.5.1.7 SPI Communication During Power-Down Mode
      2. 8.5.2 Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1  WAKEUP (0000 000x)
        2. 8.5.3.2  SLEEP (0000 001x)
        3. 8.5.3.3  SYNC (0000 010x)
        4. 8.5.3.4  RESET (0000 011x)
        5. 8.5.3.5  RDATA (0001 001x)
        6. 8.5.3.6  RDATAC (0001 010x)
        7. 8.5.3.7  SDATAC (0001 011x)
        8. 8.5.3.8  RREG (0010 rrrr, 0000 nnnn)
        9. 8.5.3.9  WREG (0100 rrrr, 0000 nnnn)
        10. 8.5.3.10 SYSOCAL (0110 0000)
        11. 8.5.3.11 SYSGCAL (0110 0001)
        12. 8.5.3.12 SELFOCAL (0110 0010)
        13. 8.5.3.13 NOP (1111 1111)
        14. 8.5.3.14 Restricted Command (1111 0001)
    6. 8.6 Register Maps
      1. 8.6.1 Register Map
      2. 8.6.2 Detailed Register Definitions
        1. 8.6.2.1  MUX0—Multiplexer Control Register 0 (address = 00h) [reset = 01h]
        2. 8.6.2.2  VBIAS—Bias Voltage Register (address = 01h) [reset = 00h]
        3. 8.6.2.3  MUX1—Multiplexer Control Register 1 (address = 02h) [reset = x0h]
        4. 8.6.2.4  SYS0—System Control Register 0 (address = 03h) [reset = 00h]
        5. 8.6.2.5  OFC—Offset Calibration Coefficient Register (address = 04h, 05h, 06h) [reset = 00h, 00h, 00h]
        6. 8.6.2.6  FSC—Full-Scale Calibration Coefficient Register (address = 07h, 08h, 09h) [reset = 00h, 00h, 40h]
        7. 8.6.2.7  IDAC0—IDAC Control Register 0 (address = 0Ah) [reset = x0h]
        8. 8.6.2.8  IDAC1—IDAC Control Register 1 (address = 0Bh) [reset = FFh]
        9. 8.6.2.9  GPIOCFG—GPIO Configuration Register (address = 0Ch) [reset = 00h]
        10. 8.6.2.10 GPIODIR—GPIO Direction Register (address = 0Dh) [reset = 00h]
        11. 8.6.2.11 GPIODAT—GPIO Data Register (address = 0Eh) [reset = 00h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Analog Input Filtering
      3. 9.1.3 External Reference and Ratiometric Measurements
      4. 9.1.4 Establishing a Proper Common-Mode Input Voltage
      5. 9.1.5 Isolated (or Floating) Sensor Inputs
      6. 9.1.6 Unused Inputs and Outputs
      7. 9.1.7 Pseudo Code Example
      8. 9.1.8 Channel Multiplexing Example
      9. 9.1.9 Power-Down Mode Example
    2. 9.2 Typical Applications
      1. 9.2.1 Ratiometric 3-Wire RTD Measurement System
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Topology
          2. 9.2.1.2.2 RTD Selection
          3. 9.2.1.2.3 Excitation Current
          4. 9.2.1.2.4 Reference Resistor (RREF)
          5. 9.2.1.2.5 PGA Setting
          6. 9.2.1.2.6 Common-Mode Input Range
          7. 9.2.1.2.7 Input and Reference Low-Pass Filters
          8. 9.2.1.2.8 Register Settings
        3. 9.2.1.3 Application Curves
      2. 9.2.2 K-Type Thermocouple Measurement (-200°C to +1250°C) With Cold-Junction Compensation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Biasing Resistors
          2. 9.2.2.2.2 Input Filtering
          3. 9.2.2.2.3 PGA Setting
          4. 9.2.2.2.4 Cold-Junction Measurement
          5. 9.2.2.2.5 Calculated Resolution
          6. 9.2.2.2.6 Register Settings
    3. 9.3 Do's and Don'ts
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
    2. 10.2 Power Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Power Supply Recommendations

The device requires two power supplies: analog (AVDD, AVSS) and digital (DVDD, DGND). The analog power supply can be bipolar (for example, AVDD = 2.5 V, AVSS = –2.5 V) or unipolar (for example, AVDD = 3.3 V, AVSS = 0 V) and is independent of the digital power supply. The digital supply sets the digital I/O levels (with the exception of the GPIO levels that are set by the analog supply of AVDD to AVSS).

10.1 Power Supply Sequencing

The power supplies can be sequenced in any order but in no case must any analog or digital inputs exceed the respective analog or digital power-supply voltage limits. Wait at least 216 tCLK cycles after all power supplies are stabilized before communicating with the device to allow the power-on reset process to complete.

10.2 Power Supply Decoupling

Good power-supply decoupling is important to achieve optimum performance. AVDD, AVSS (when using a bipolar supply), and DVDD must be decoupled with at least a 0.1-µF capacitor, as shown in Figure 77. Place the bypass capacitors as close to the power-supply pins of the device as possible using low-impedance connections. Use multi-layer ceramic chip capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting the capacitors to the device pins can offer superior noise immunity. The use of multiple vias in parallel lowers the overall inductance and is beneficial for connections to ground planes. Connect analog and digital ground together as close to the device as possible.

ADS1148-Q1 ai_power_sup_decoup_sbas674.gif Figure 77. Power-Supply Decoupling for Unipolar and Bipolar Supply Operation
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