Table 3. PGA Full-Scale Range

8.3.2.1 PGA Common-Mode Voltage Requirements

To stay within the linear operating range of the PGA, the input signals must meet certain requirements that are discussed in this section.

The outputs of both amplifiers (A1 and A2) in Figure 18 cannot swing closer to the supplies (AVSS and AVDD) than 100 mV. If the outputs OUT_P and OUT_N are driven to within 100 mV of the supply rails, the amplifiers saturate and consequently become nonlinear. To prevent this nonlinear operating condition, the output voltages must meet Equation 5.

Translating the requirements of Equation 5 into requirements referred to the PGA inputs (AIN_P and AIN_N) is beneficial because there is no direct access to the outputs of the PGA. The PGA employs a symmetrical design; therefore, the common-mode voltage at the output of the PGA can be assumed to be the same as the common-mode voltage of the input signal, as shown in Figure 19.

Figure 19. PGA Common-Mode Voltage

The common-mode voltage is calculated using Equation 6.

The voltages at the PGA inputs (AIN_P and AIN_N) can be expressed as Equation 7 and Equation 8.

The output voltages (V_(OUTP) and V_(OUTN)) can then be calculated as Equation 9 and Equation 10.

The requirements for the output voltages of amplifiers A1 and A2 (Equation 5) can now be translated into requirements for the input common-mode voltage range using Equation 9 and Equation 10, which are given in Equation 11 and Equation 12.

To calculate the minimum and maximum common-mode voltage limits, the maximum differential input voltage (V_{IN (MAX)}) that occurs in the application must be used. V_{IN (MAX)} can be less than the maximum possible full-scale value.

8.3.2.2 PGA Common-Mode Voltage Calculation Example

The following paragraphs explain how to apply Equation 11 and Equation 12 to a hypothetical application. The setup for this example is AVDD = 3.3 V, AVSS = 0 V, and gain = 16, using an external reference of V_REF = 2.5 V. The maximum possible differential input voltage V_IN = (V_(AINP) – V_(AINN)) that can be applied is then limited to the full-scale range of FSR = ±2.5 V / 16 = ±0.156 V. Consequently, Equation 11 and Equation 12 yield an allowed V_CM range of 1.35 V ≤ V_CM ≤ 1.95 V.

If the sensor signal connected to the inputs in this hypothetical application does not make use of the entire full-scale range but is limited to V_{IN (MAX)} = ±0.1 V, for example, then this reduced input signal amplitude relaxes the V_CM restriction to 0.9 V ≤ V_CM ≤ 2.4 V.

In the case of a fully differential sensor signal, each input (AIN_P, AIN_N) can swing up to ±50 mV around the common-mode voltage (V_(AINP) + V_(AINN)) / 2, which must remain between the limits of 0.9 V and 2.4 V. The output of a symmetrical wheatstone bridge is an example of a fully differential signal. Figure 20 shows a situation where the common-mode voltage of the input signal is at the lowest limit. V_(OUTN) is exactly at 0.1 V in this case. Any further decrease in common-mode voltage (V_CM) or increase in differential input voltage (V_IN) drives V_(OUTN) below 0.1 V and saturates amplifier A2.

Figure 20. Example Where V_CM is at the Lowest Limit

In contrast, the signal of a resistance temperature detector (RTD) is of a pseudo-differential nature (if implemented as in the 3-Wire RTD Measurement System section), where the negative input is held at a constant voltage other than 0 V and only the voltage on the positive input changes. When a pseudo-differential signal must be measured, the negative input in this example must be biased at a voltage from 0.85 V to 2.35 V. The positive input can then swing up to V_{IN (MAX)} = 100 mV above the negative input. In this case, the common-mode voltage changes at the same time that the voltage on the positive input changes. That is, when the input signal swings between 0 V ≤ V_IN ≤ V_{IN (MAX)}, the common-mode voltage swings between V_(AINN) ≤ V_CM ≤ V_(AINN) + ½ V_{IN (MAX)}. Satisfying the common-mode voltage requirements for the maximum input voltage V_{IN (MAX)} ensures the requirements are met throughout the entire signal range.

Figure 21 and Figure 22 show examples of both fully differential and pseudo-differential signals, respectively.

Figure 21. Fully Differential Input Signal

Figure 22. Pseudo-Differential Input Signal

8.3.2.3 Analog Input Impedance

The device inputs are buffered through a high-input impedance PGA before reaching the ΔΣ modulator. For the majority of applications, the input current is minimal and can be neglected. However, because the PGA is chopper-stabilized for noise and offset performance, the input impedance is best described as a small absolute input current. The absolute input current for selected channels is approximately proportional to the selected modulator clock. Table 4 shows the typical values for these currents with a differential voltage coefficient and the corresponding input impedances over data rate.

Table 5. Modulator Clock Frequency for Different Data Rates

Table 6. Digital Filter Specifications⁽¹⁾

Table 7. Internal Reference Settling Time

Table 8. Bias Voltage Settling Time

8.3.12.1 Power-Supply Monitor

The system monitor can measure the analog or digital power supply. When measuring the power supply (V_SP), the resulting conversion is approximately 1/4 of the actual power supply voltage, as shown in Equation 15.

8.3.12.2 External Voltage Reference Monitor

The ADC can measure the external voltage reference. In this configuration, the monitored external voltage reference (V_REX) is connected to the analog input. The result (conversion code) is approximately 1/4 of the actual reference voltage, as shown in Equation 16.

8.3.12.3 Ambient Temperature Monitor

On-chip diodes provide temperature-sensing capability. When selecting the temperature monitor function, the anodes of two diodes are connected to the ADC. Typically, the difference in diode voltage is 118 mV at
T_A = 25°C with a temperature coefficient of 405 µV/°C.

Table 9. START Pin Conversion Times for Figure 36 ⁽¹⁾

8.4.4.1 Settling Time for Channel Multiplexing

The device is a true single-cycle settling ΔΣ converter. The first data available after the start of a conversion are fully settled and valid for use, provided that the input signal has settled to the final result. The time required to settle is roughly equal to the inverse of the data rate. The exact time depends on the specific data rate and the operation that resulted in the start of a conversion; see Table 10 for specific values.

8.4.4.2 Channel Cycling and Overload Recovery

When cycling through channels, take care when configuring the device to ensure that settling occurs within one cycle. For setups that cycle through MUX channels, but do not change PGA and data rate settings, changing the MUX0 register is sufficient. However, when changing PGA and data rate settings, ensure that an overload condition cannot occur during the data transmission. When configuration register data are transferred to the device, new settings become active at the end of each byte sent. Therefore, a brief overload condition can occur during the transmission of configuration data after the completion of the MUX0 byte and before the completion of the SYS0 byte. This temporary overload can result in intermittent incorrect readings. To ensure that an overload does not occur, the communication may need to be split into two separate communications, thus allowing the SYS0 register to before the change of the MUX0 register.

In the event of an overloaded state, take care to ensure single-cycle settling into the next cycle. Changing data rates during an overload state can cause the chopper to become unstable because the device implements a chopper-stabilized PGA. This instability results in slow settling time. To prevent this slow settling, always change the PGA setting or MUX setting to a non-overloaded state before changing the data rate.

8.4.4.3 Single-Cycle Settling

The ADS1148-Q1 is capable of single-cycle settling across all gains and data rates. However, to achieve single-cycle settling at 2 kSPS, special care must be taken with respect to the interface using WREG to change a configuration register. When operating at 2 kSPS, the SCLK period must not exceed 520 ns, and the time between beginning to write a register byte data and the beginning of a subsequent register byte data must not exceed 4.2 µs. Additionally, when performing multiple individual write commands to the first four registers, wait at least 64 oscillator clocks before initiating another write command.

8.4.4.4 Digital Filter Reset Operation

Apart from the RESET command and the RESET pin, the digital filter is reset automatically when either a write operation to the MUX0, VBIAS, MUX1, or SYS0 registers is performed, when a SYNC command is issued, or when the START pin is taken high.

The filter is reset four system clocks (t_CLK) after the falling edge of the seventh SCLK of the SYNC command. Similarly, if any write operation takes place in the MUX0 register, regardless of whether the register value changed or not, the filter is reset after the completion of the MUX0 write.

If any write activity takes place in the VBIAS, MUX1, or SYS0 registers, regardless of whether the register value changed or not, the filter is reset. The reset pulse lasts for 32 modulator clocks after the completion of the write operation. If there are multiple write operations, the resulting reset pulse may be viewed as the ANDed result of the different active low pulses created individually by each action.

Table 10 lists the conversion time after a filter reset. Note that this time depends on the operation initiating the reset. Also, the first conversion after a filter reset has a slightly different time than the second and subsequent conversions.

8.4.5.1 Offset Calibration Register: OFC[2:0]

The offset calibration is a 24-bit word, composed of three 8-bit registers. The offset is in twos complement format with a maximum positive value of 7FFFFFh and a maximum negative value of 800000h. The upper 16 bits, OFC[2:1], are the most important bits of the offset calibration register for calibration and can correct offsets ranging from –FS to +FS, as shown in Table 11. The lower eight bits, OFC[0], provide sub-LSB correction and are used by the calibration commands. If a calibration command is issued and the offset register is then read for storage and re-use later, all 24 bits of the OFC are recommended to be used. When the calibration commands are not used and the offset is corrected by writing a user-calculated value to the OFC register, only OFC[2:1] are recommended to be used and OFC[0] is recommended to be left as all zeros. A register value of 000000h provides no offset correction.

Note that although the offset calibration register value can correct offsets ranging from –FS to +FS (as shown in Table 11), avoid overloading the analog inputs.

8.4.5.2 Full-Scale Calibration Register: FSC[2:0]

The full-scale or gain calibration is a 24-bit word composed of three 8-bit registers. The full-scale calibration value is 24 bits, straight binary, and normalized to 1.0 at code 400000h. Table 12 summarizes the scaling of the full-scale register. Note that although the full-scale calibration register can correct gain errors greater than 1 (with gain scaling less than 1), make sure to avoid overloading the analog inputs.

8.4.5.3 Calibration Commands

The device provides commands for three types of calibration: system gain calibration, system offset calibration, and self offset calibration. Where absolute accuracy is required, a calibration is recommended to be performed after power up, a change in temperature, a change of gain, and in some cases a change in channel. At the completion of calibration the DRDY signal goes low, indicating that the calibration is complete. The first data after calibration are always valid. If the START pin is taken low or a SLEEP command is issued after any calibration command, the device powers down after completing calibration.

After a calibration starts, allow the calibration to complete before issuing any other commands (other than the SLEEP command). Issuing commands during a calibration can result in corrupted data. If this scenario occurs, either resend the calibration command that was aborted or issue a device reset.

8.4.5.4 Calibration Timing

When calibration is initiated, the device performs 16 consecutive data conversions and averages the results to calculate the calibration value. This process provides a more accurate calibration value. The time required for calibration is shown in Table 13 and can be calculated using Equation 19.

Equation 19.

8.5.1.1 Chip Select (CS)

The CS pin activates SPI communication. CS must be low before data transactions and must stay low for the entire SPI communication period. When CS is high, the DOUT/DRDY pin enters a high-impedance state. Therefore, reads and writes to the serial interface are ignored and the serial interface is reset. The DRDY pin operation is independent of CS. DRDY still indicates when a new conversion completes and is forced high in response to SCLK, even if CS is high.

Taking CS high only deactivates the SPI communication with the device. Data conversion continues and the DRDY signal can be monitored to check if a new conversion result is ready. A master device monitoring the DRDY signal can select the appropriate slave device by pulling the CS pin low.

8.5.1.2 Serial Clock (SCLK)

SCLK provides the clock for serial communication. SCLK is a Schmitt-trigger input, but SCLK is recommended to be kept as free from noise as possible to prevent glitches from inadvertently shifting the data. Data are shifted into DIN on the falling edge of SCLK and are shifted out of DOUT on the SCLK rising edge.

8.5.1.3 Data Input (DIN)

DIN is used along with SCLK to send data to the device. Data on DIN are shifted into the device on the SCLK falling edge.

The communication of this device is full-duplex in nature. The device monitors commands shifted in even when data are being shifted out. Data that are present in the output shift register are shifted out when sending in a command. Therefore, make sure that whatever is being sent on the DIN pin is valid when shifting out data. When no command is sent to the device when reading out data, send the no operation command (NOP) command on DIN.

8.5.1.4 Data Ready (DRDY)

The DRDY pin goes low to indicate that a new conversion is complete, and the conversion result is stored in the conversion result buffer. SCLK must be held low for t_DTS after the DRDY low transition (see Figure 2) so that the conversion result is loaded into both the result buffer and the output shift register. Therefore, do not issue commands during this time frame if the conversion result is to be read out later. This constraint applies only when CS is asserted and the device is in RDATAC mode. When CS is not asserted, SPI communication with other devices on the SPI bus does not affect loading of the conversion result. After the DRDY pin goes low, DRDY is forced high on the first falling edge of SCLK (so that the DRDY pin can be polled for 0 instead of waiting for a falling edge). If the DRDY pin is not taken high by clocking in SCLKs after DRDY falls low, a short high pulse for a duration of t_PWH indicates that new data are ready.

8.5.1.5 Data Output and Data Ready (DOUT/DRDY)

The DOUT/DRDY pin has two modes: data out (DOUT) only, or DOUT combined with data ready (DRDY). The DRDY MODE bit determines the function of this pin and can be found in the IDAC0 register. In either mode, the DOUT/DRDY pin goes to a high-impedance state when CS is taken high.

When the DRDY MODE bit is set to 0, this pin functions as DOUT only. Data are clocked out on the SCLK rising edge, MSB first (as shown in Figure 39).

When the DRDY MODE bit is set to 1, this pin functions as both DOUT and DRDY. Data are shifted out as with DOUT, but the pin adds the DRDY function. Note that this mode is not operational when the device is in stop read data continuous mode when the SDATAC command is given.

The DRDY MODE bit modifies only the DOUT/DRDY pin functionality. The DRDY pin functionality remains unaffected.

8.5.1.6 SPI Reset

SPI communication is reset in several ways. To reset the serial interface (without resetting the registers or the digital filter), the CS pin can be pulled high. Taking the RESET pin low resets the serial interface along with all the other digital functions. This process also returns all registers to the default values and starts a new conversion.

In systems where CS is tied low permanently, register writes must always be fully completed in 8-bit increments. If a glitch on SCLK disrupts SPI communications, commands are not recognized by the device. The device implements a timeout function for all listed commands in the Commands section in the event that data are corrupted and the CS pin is permanently tied low. The SPI timeout resets the interface if idle for 64 conversion cycles.

8.5.1.7 SPI Communication During Power-Down Mode

When the START pin is low or the device is in power-down mode, only the RDATA, RDATAC, SDATAC, WAKEUP, and NOP commands can be issued. The RDATA command can be used to repeatedly read the last conversion result during power-down mode. Other commands do not function because the internal clock is shut down to save power during power-down mode.

Table 14. Ideal Output Code vs Input Signal

Table 15. SPI Commands

8.5.3.1 WAKEUP (0000 000x)

Use the WAKEUP command to power up the device after a SLEEP command. After execution of the WAKEUP command, the device powers up on the falling edge of the eighth SCLK.

8.5.3.2 SLEEP (0000 001x)

The SLEEP command places the device into power-down mode. When the SLEEP command is issued, the device completes the current conversion and then goes into power-down mode. Note that this command does not automatically power down the internal voltage reference; see the VREFCON bits in the MUX1 section for each device for further details.

To exit power-down mode, issue the WAKEUP command. Single conversions can be performed by issuing a WAKEUP command followed by a SLEEP command.

Both WAKEUP and SLEEP are the software command equivalents of using the START pin to control the device; see Figure 44.

Figure 44. SLEEP and WAKEUP Commands Operation

8.5.3.3 SYNC (0000 010x)

The SYNC command resets the ADC digital filter and starts a new conversion. The DRDY pin from multiple devices connected to the same SPI bus can be synchronized by issuing a SYNC command to all devices simultaneously.

Figure 45. SYNC Command Operation

8.5.3.4 RESET (0000 011x)

The RESET command restores the registers to the respective default values. This command also resets the digital filter. RESET is the command equivalent of using the RESET pin to reset the device. However, the RESET command does not reset the serial interface. If the RESET command is issued when the serial interface is out of synchronization because of a glitch on SCLK, the device does not reset. The CS pin can be used to reset the serial interface first, and then a RESET command can be issued to reset the device. The RESET command holds the registers and the decimation filter in a reset state for 0.6 ms when the system clock frequency is 4.096 MHz, similar to the hardware reset. Therefore, SPI communication can only be started 0.6 ms after the RESET command is issued, as shown in Figure 46.

Figure 46. SPI Communication after an SPI Reset

8.5.3.5 RDATA (0001 001x)

The RDATA command loads the most recent conversion result into the output register. After issuing this command, the conversion result is read out by sending 16 SCLKs, as shown in Figure 47. This command also works in RDATAC mode.

Figure 47. RDATA: Reading Data Once Command

When performing multiple reads of the conversion result, the RDATA command can be sent when the last eight bits of the conversion result are shifted out during the course of the first read operation by taking advantage of the duplex communication nature of the serial interface, as shown in Figure 48.

Figure 48. Using RDATA in Full-Duplex Mode

8.5.3.6 RDATAC (0001 010x)

The RDATAC command enables the read data continuous mode. This mode is the default mode after power-up or reset. In read data continuous mode, new conversion results are automatically loaded onto DOUT. The conversion result can be received from the device after the DRDY signal goes low by sending 16 SCLKs. Reading back all the bits is not necessary, as long as the number of bits read out is a multiple of eight. The RDATAC command must be issued after DRDY goes low and the command takes effect on the next DRDY, as shown in Figure 49.

Be sure to complete data retrieval (conversion result or register read back) before DRDY returns low, otherwise the resulting data are corrupted. Successful register read operations in RDATAC mode require the knowledge of when the next DRDY falling edge occurs.

Figure 49. RDATAC: Read Data Continuously Command

8.5.3.7 SDATAC (0001 011x)

The SDATAC command terminates read data continuous mode. In stop read data continuous mode, the conversion result is not automatically loaded onto DOUT when DRDY goes low, and register read operations can be performed without interruption from new conversion results being loaded into the output shift register. Use the RDATA command to retrieve conversion data. The SDATAC command takes effect after the next DRDY.

If DRDY is not actively monitored for data conversions, the stop read data continuous mode is the preferred method of reading data. In this mode, a read of ADC data is not interrupted by the completion of a new ADC conversion.

8.5.3.8 RREG (0010 rrrr, 0000 nnnn)

The RREG command outputs the data from up to 15 registers, starting with the register address specified as part of the instruction. The number of registers read is one plus the value of the second byte. If the count exceeds the remaining registers, the addresses wrap back to the beginning. The 2-byte command structure for RREG is listed below.

• First Command Byte: 0010 rrrr, where rrrr is the address of the first register to read.
• Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to read –1.
• Byte: data read from the registers are clocked out with NOPs.

The full-duplex nature of the serial interface cannot be used when reading out register data. For example, a SYNC command cannot be issued when reading out the VBIAS and MUX1 data, as shown in Figure 50. Any command sent during the readout of the register data is ignored. Thus, NOPs are recommended to be sent through DIN when reading out register data.

Figure 50. RREG: Read from Register Command

8.5.3.9 WREG (0100 rrrr, 0000 nnnn)

The WREG command writes to the registers, starting with the register specified as part of the instruction. The number of registers that are written is one plus the value of the second byte. The command structure for WREG is:

• First Command Byte: 0100 rrrr, where rrrr is the address of the first register to be written.
• Second Command Byte: 0000 nnnn, where nnnn is the number of bytes to be written – 1.
• Byte: data to be written to the registers.

Figure 51. WREG: Write to Register Command

8.5.3.10 SYSOCAL (0110 0000)

The SYSOCAL command initiates a system offset calibration. For a system offset calibration, the inputs must be externally shorted to a voltage within the input common-mode range. The inputs must be near the mid-supply voltage of (AVDD + AVSS) / 2. The OFC register is updated when the command completes. Timing for the calibration commands is shown in Figure 52.

Figure 52. Calibration Command

8.5.3.11 SYSGCAL (0110 0001)

The SYSGCAL command initiates the system gain calibration. For a system gain calibration, the input must be set to full-scale. The FSC register is updated after this operation. Timing for the calibration commands is shown in Figure 52.

8.5.3.12 SELFOCAL (0110 0010)

The SELFOCAL command initiates a self offset calibration. The device internally shorts the inputs to mid-supply and performs the calibration. The OFC register is updated after this operation. Timing for the calibration commands is shown in Figure 52.

8.5.3.13 NOP (1111 1111)

This command is a no-operation command. NOP is used to clock out data without clocking in a command.

8.5.3.14 Restricted Command (1111 0001)

This command is a restricted command. This command must never be issued to the device.

Table 16. Register Map

8.6.2.1 MUX0—Multiplexer Control Register 0 (address = 00h) [reset = 01h]

This register allows any combination of differential inputs to be selected on any of the input channels. Note that this setting can be superceded by the MUXCAL and VBIAS bits.

8.6.2.2 VBIAS—Bias Voltage Register (address = 01h) [reset = 00h]

8.6.2.3 MUX1—Multiplexer Control Register 1 (address = 02h) [reset = x0h]

Table 20 provides the ADC input connection and PGA settings for each MUXCAL setting. The PGA setting reverts to the original SYS0 register setting when MUXCAL is taken back to normal operation or offset measurement.

8.6.2.4 SYS0—System Control Register 0 (address = 03h) [reset = 00h]

8.6.2.5 OFC—Offset Calibration Coefficient Register (address = 04h, 05h, 06h) [reset = 00h, 00h, 00h]

These bits make up the offset calibration coefficient register. Note that address 04h = 7-0, 05h = 15-8, and 06h = 23-16.

8.6.2.6 FSC—Full-Scale Calibration Coefficient Register (address = 07h, 08h, 09h) [reset = 00h, 00h, 40h]

These bits make up the full-scale calibration coefficient register. Note that address 07h = 7-0, 08h = 15-8, and 09h = 23-16.

8.6.2.7 IDAC0—IDAC Control Register 0 (address = 0Ah) [reset = x0h]

8.6.2.8 IDAC1—IDAC Control Register 1 (address = 0Bh) [reset = FFh]

The two IDACs can be routed to either the IEXC1 and IEXC2 output pins or directly to the analog inputs.

8.6.2.9 GPIOCFG—GPIO Configuration Register (address = 0Ch) [reset = 00h]

8.6.2.10 GPIODIR—GPIO Direction Register (address = 0Dh) [reset = 00h]

8.6.2.11 GPIODAT—GPIO Data Register (address = 0Eh) [reset = 00h]