ZHCSGA6A February 2017 – June 2017 ADS114S06 , ADS114S08
PRODUCTION DATA.
The ADS114S0x incorporates a power-on reset circuit that holds the device in reset until all supplies reach approximately 1.65 V. The power-on reset also ensures that the device starts operating in a known state in case a brown-out event occurs, when the supplies have dipped below the minimum operating voltages. When the device completes a POR sequence, the FL_POR flag in the status register is set high to indicate that a POR has occurred.
Begin communications with the device 2.2 ms after the power supplies reach minimum operating voltages. The only exception is polling the status register for the RDY bit. If the user polls the RDY bit, then use an SCLK rate of half the maximum-specified SCLK rate to get a proper reading when the device is making internal configurations. This 2.2-ms POR time is required for the internal oscillator to start up and the device to properly set internal configurations. After the internal configurations are set, the device sets the RDY bit in the device status register (01h). When this bit is set to 0, user configurations can be programmed into the device. Figure 83 shows the power-on reset timing sequence for the device.