The analog input of the ADC is differential, with the input defined as a difference voltage: V_IN = V_AINP – V_AINN. For best performance, drive the input with a differential signal with the common-mode voltage centered to mid-supply (AVDD1 + AVSS) / 2.

The ADC can accept either unipolar or bipolar input signals by configuring AVDD1 and AVSS accordingly. Figure 8-1 shows an example of a differential signal with the supplies configured to unipolar operation. Symmetric input voltage headroom is available when the common-mode voltage is at mid-supply (AVDD1 / 2). Use AVDD1 = 5 V and AVSS = 0 V for unipolar operation (AVDD1 can be reduced to 3 V in low-speed mode). The VCM output provides a buffered common-mode voltage to level-shift the output voltage in the external driver stage. Figure 8-2 shows an example of a differential signal configured for bipolar operation. The common-mode voltage of the signal is normally at 0 V. Use AVDD1 and AVSS = ±2.5 V for bipolar operation (AVDD and AVSS can be reduced to ±1.5 V in low-speed mode).

Figure 8-1 Unipolar Differential Input Signal

Figure 8-2 Bipolar Differential Input Signal

In both bipolar and unipolar power-supply configurations, the ADC can accept single-ended input signals by tying the AINN input to AVSS or ground, or to mid-supply. However, because AINN is now a fixed voltage, the voltage range of the ADC is limited by the input swing range of AINP (±2.5 V or 0 V to 5 V for a 5-V supply).

The simplified circuit of Figure 8-3 represents the analog input structure.

Diodes protect the ADC inputs from electrostatic discharge (ESD) events that occur during the manufacturing process and during printed circuit board (PCB) assembly when manufactured in an ESD-controlled environment. If the inputs are driven below AVSS – 0.3 V, or above AVDD1 + 0.3 V, the protection diodes may conduct. If these conditions are possible, use external clamp diodes, series resistors, or both to limit the input current to the specified value.

The input multiplexer offers the option of normal or reverse input signal polarities. The multiplexer also provides two internal test modes to help verify ADC performance. The offset test mode is used to verify noise and offset error by providing a short to the ADC inputs. The resulting noise and offset voltage data are evaluated by the user. CMRR performance is tested using the CMRR test mode by applying a CMRR test signal to the AINP input. The resulting CMRR test data are also evaluated by the user. Table 8-1 shows the switch configurations of the input multiplexer circuit of Figure 8-3.

The device has optional input precharge buffers to reduce the charge required by capacitor C_IN during the input sampling phase. When the capacitor is near full charge, the precharge buffers are bypassed (S₇ and S₈ of Figure 8-3 in up positions). The external signal driver then provides the fine charge to the capacitor. At the completion of the sample phase, the sampling capacitor is discharged by the modulator to complete the cycle, at which time the sample process repeats. The buffers reduce the transient input current required to charge C_IN, therefore reducing the settling time requirement of the signal. Incomplete settling of the input signal can lead to degraded ADC performance. The input buffers are enabled by the AINP_BUF and AINN_BUF bits of the CONFIG1 register. In many cases, if AINN is tied to ground or to a low-impedance fixed potential, the AINN buffer can be disabled to reduce power consumption.

With the input precharge buffers disabled, the charge required by the input sampling capacitor can be modeled as an average input current flowing into the ADC inputs. As shown in Equation 11 and Equation 12, the input current is comprised of differential and absolute components.

where:

• f_MOD = f_CLK / 2 = 12.8 MHz (high-speed mode), 1.6 MHz (low-speed mode)
• C_IN = 7.4 pF (1x input range), 3.6 pF (2x input range)

where:

• f_MOD = f_CLK / 2 = 12.8 MHz (high-speed mode), 1.6 MHz (low-speed mode)
• C_CM = 0.35 pF (1x input range), 0.17 pF (2x input range)

For f_MOD = 12.8 MHz, C_IN = 7.4 pF, and C_CM = 0.35 pF, the input current resulting from differential voltage is 95 μA/V and the input current resulting from the absolute voltage is 4.5 μA/V. For example, if AINP = 4.5 V and AINN = 0.5 V, then V_IN = 4 V. The total AINP input current = (4 V · 95 μA/V) + (4.5 V · 4.5 μA/V) = 400 μA, and the total AINN current is (–4 V · 95 μA/V) + (0.5 V · 4.5 μA/V) = –378 μA.

The charge demand of the input sampling capacitor requires the signal to settle within a half cycle at the modulator frequency t = 1 / (2 · f_MOD). To satisfy this requirement, the driver bandwidth is typically required to be much larger than the original signal frequency. The bandwidth of the driver can be determined to be sufficient when the THD and SNR data sheet performance are achieved. In the low-speed mode of operation, the modulator sampling is eight times slower, therefore more time is available for driver settling.