To operate the ADC with an external clock, apply the clock signal to the CLK pin, then program the CLK_SEL bit to 1b. A divide-by-eight option is available to operate the ADC in low-speed mode using the high-speed mode clock frequency (set the CLK_DIV bit = 1b). The clock can be decreased from nominal to yield specific data rates between the integer OSR values. However, the conversion noise when operating at the reduced clock frequency is the same as the higher clock frequency. Reducing the conversion noise is only possible by increasing the OSR value or changing the filter mode.

Clock jitter results in timing variations at the modulator sampling instant and if excessive, can lead to degraded SNR performance. Thus, use a low-jitter clock signal free of noise from other signals. For example, with a 200-kHz signal frequency, use an external clock with < 20-ps (rms) jitter. For lower signal frequencies, the clock jitter requirement can be relaxed by –20 dB per decade of signal frequency. For example, with f_IN = 20 kHz, a clock with 200-ps jitter can be tolerated. Many types of RC oscillators exhibit high levels of jitter and must be avoided for ac signal measurement. Instead, use a crystal-based clock oscillator for the clock signal. Avoid ringing on the clock signal. A series resistor placed at the output of the clock buffer often helps reduce ringing.