In simultaneous-sampling systems using multiple ADCs, the devices can be connected in a daisy-chain string to reduce the number of SPI connections. A daisy-chain connection links together the SPI output of one device to the SPI input of the next device so the devices in the chain appear as a single logical device to the host controller. There is no special programming required for daisy-chain operation, simply apply additional shift clocks to access all devices in the chain. For simplified operation, program the same SPI frame size for each device (for example, when enabling the CRC option of all devices, thus producing a 24-bit frame size).

Figure 8-36 illustrates four devices connected in a daisy-chain configuration. The SDI of ADS117L11 (1) connects to the host SPI data out, and SDO/DRDY of ADS117L11 (4) connects to the host SPI data input. The shift operation is simultaneous for all devices in the chain. After each ADC shifts out the conversion data, the data of SDI appears on SDO/DRDY to drive the SDI of the next device in the chain. The shift operation continues until the last device in the chain is reached. The SPI frame ends when CS is taken high, at which time the data shifted into each device is interpreted. The SDO/DRDY pin must be programmed to data output-only mode.

Figure 8-37 shows the initial communication using 16-bit frame size for each device after device power up.

To input data, the host first shifts in the data intended for the last device in the chain. The number of input bytes for each ADC is sized to match the output frame size. The default frame size is 16 bits (CRC and STATUS byes are default off), so initially each ADC requires two command bytes. The input data of ADC (4) is first, followed by the input data of ADC (3), and so forth.

Figure 8-38 shows the detailed input data sequence for the daisy-chain write register operation of Figure 8-36. 32-bit frames for each ADC are shown (16 bits of data, with the STATUS and CRC bytes enabled). Command operations can be different for each ADC. The read register operation requires a second frame operation to read out the register data.

Figure 8-39 illustrates the clock sequence to read conversion data from the device connection in Figure 8-36. This example illustrates a 24-bit output frame (16-bits of data, with the CRC byte enabled). The output data of ADC (4) is first in the sequence, followed by the data of ADC (3), and so on. The total number of clocks required to shift out the data is given by the number of bits per frame × the number of devices in the chain. In this example, 24-bit output frames × four devices result in 96 total clocks.

As shown in Equation 17, the maximum number of devices connected in daisy-chain configuration is limited by the SCLK signal frequency, data rate, and number of bits per frame. The same limitation applies to parallel-connected SPI because the data from each ADC is also read sequentially.

For example, if f_SCLK = 20 MHz, f_DATA = 100 kSPS, and the maximum length 32-bit frames are used, the maximum number of daisy-chain connected devices is the floor of: ⌊20 MHz / (100 kHz · 32)⌋ = 6.