The ADC has three analog power supplies and one digital power supply. Power-supply voltages AVDD1 and AVSS establish the type of analog input signal range. Bipolar input signals are only possible using bipolar supply voltages, such as AVDD1 = 2.5 V and AVSS = –2.5 V, and only unipolar input signals are possible using unipolar supply voltages, such as AVDD1 = 5 V and AVSS = DGND.

The AVDD2 power-supply voltage is with respect to AVSS and the IOVDD power-supply voltage is with respect to DGND. The specified range of the power supplies are listed in the Section 6.3 table. The ADC can be operated using a single 5-V voltage for all supplies (or one 3-V voltage in low-speed mode) with AVSS = DGND. The ADC supply pins must always have separate bypass capacitors.

Power-supply bypassing at the device pins is essential to achieve data sheet performance. The ADC also requires capacitors for the CAPA and CAPD pins, and for the analog input and reference pins. Place the capacitors close to the device pins using short, direct traces with the smaller capacitor value placed closest to the device pins.

The recommended bypass components of the device pins are as follows:

1. AVDD1 to AVSS:
   1. Parallel combination of 1-µF and 0.1-µF capacitors across the AVDD1 power supply and AVSS
   2. A 3-Ω resistor placed in series between the bypass capacitors and the device AVDD1 pin
2. AVDD2 to AVSS: Parallel combination of 1-µF and 0.1-µF capacitors across the pins
3. IOVDD to DGND: Parallel combination of 1-µF and 0.1-µF capacitors across the pins
4. CAPA to AVSS: 1-µF capacitor placed across the pins
5. CAPD to DGND: 1-µF capacitor placed across the pins
6. REFP, REFN: Parallel combination of 1-µF and 0.1-µF capacitors across the pins
7. AINP, AINN: 22-Ω resistors in series, followed by 2.2 nF across the pins, 220 pF from each pin to AVSS

Figure 9-4 shows the component placement for the device configured for unipolar power-supply operation.

The power supplies do not require special sequencing and can be powered up in any order, but in no case must any analog or digital input exceed the respective AVDD1 and AVSS (analog) or IOVDD (digital) power-supply voltages. An internal reset is performed after the IOVDD power-supply voltage is applied.