The ADC has the option of 3-wire SPI operation by grounding CS. 3-wire mode is detected by the ADC when CS is grounded at power up or after reset. 3-wire SPI mode is indicated by bit 7 (CS_MODE) of the STATUS register. The device changes to 4-wire SPI mode any time CS is taken high.

Because CS no longer controls frame timing in 3-wire SPI mode, SCLKs are counted by the ADC to determine the beginning and ending of a frame. The number of SCLK bits must be controlled by the host and must match the size of the output frame. The number of bits per frame depends on device configuration. The size of the output frame is listed in Table 8-11. Because frame timing is determined by the number of SCLKs, avoid inadvertent SCLK transitions, such as those possibly occurring at power up.

3-wire SPI mode supports the same command format and clocking as the 4-wire mode, except there is no CS toggling and therefore no wait time between frames.