ZHCSQZ9A March 2022 – October 2022 ADS117L11
PRODUCTION DATA
The SPI cyclic redundancy check (CRC) is an SPI check code used to detect transmission errors to and from the host controller. A CRC byte is transmitted with the ADC input data by the host and a CRC byte is transmitted with the output data by the ADC. The SPI CRC error check is enabled by the SPI_CRC bit of the CONFIG4 register.
The CRC code is calculated by the host on the two command bytes. Any input bytes padded to the start of the frame are not included in the CRC calculation. The ADC checks the input command CRC code against an internal code calculated over the two input command bytes. If the CRC codes do not match, the command is not executed and the SPI_ERR bit is set in the STATUS byte. Register write operations are blocked except to the STATUS register to allow clearing the SPI CRC error by writing 1b to the SPI_ERR bit. Register read operations are not blocked unless an SPI_CRC error is detected in the immediately preceding register-read command frame.
The number of bytes used to calculate the output CRC code depends on the amount of data bytes transmitted in the frame. All data bytes that precede the output CRC code are used in the CRC calculation. Table 8-12 shows the number of bytes used for the output CRC calculation.
BYTE COUNT | BYTE FIELD DESCRIPTION |
---|---|
2 | 16 bits of conversion data |
2 | One byte of register data + 00h pad byte |
3 | 16 bits of conversion data + STATUS byte |
3 | One byte of register data + two 00h pad bytes |
The CRC code calculation is the 8-bit remainder of the bitwise exclusive-OR (XOR) operation of the variable length argument with the CRC polynomial. The CRC is based on the CRC-8-ATM (HEC) polynomial: X8 + X2 + X1 + 1. The nine coefficients of the polynomial are: 100000111. The input argument is XOR'd with FFh allowing error detection in the event that SDI and SDO/DRDY fail high or fail low.
The following procedure is used to compute the CRC code value: