ZHCSII0A July   2018  – November 2018 ADS1219

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      电压、电流和温度监控应用
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 I2C Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Multiplexer
      2. 8.3.2 Rail-to-Rail Input Buffers and Programmable Gain Stage
      3. 8.3.3 Voltage Reference
      4. 8.3.4 Modulator and Internal Oscillator
      5. 8.3.5 Digital Filter
      6. 8.3.6 Conversion Times
      7. 8.3.7 Offset Calibration
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. 8.4.1.1 Power-On Reset
        2. 8.4.1.2 RESET Pin
        3. 8.4.1.3 Reset by Command
      2. 8.4.2 Conversion Modes
        1. 8.4.2.1 Single-Shot Conversion Mode
        2. 8.4.2.2 Continuous Conversion Mode
      3. 8.4.3 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
        1. 8.5.1.1 I2C Address
        2. 8.5.1.2 Serial Clock (SCL) and Serial Data (SDA)
        3. 8.5.1.3 Data Ready (DRDY)
        4. 8.5.1.4 Interface Speed
        5. 8.5.1.5 Data Transfer Protocol
        6. 8.5.1.6 I2C General Call (Software Reset)
        7. 8.5.1.7 Timeout
      2. 8.5.2 Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1 Command Latching
        2. 8.5.3.2 RESET (0000 011x)
        3. 8.5.3.3 START/SYNC (0000 100x)
        4. 8.5.3.4 POWERDOWN (0000 001x)
        5. 8.5.3.5 RDATA (0001 xxxx)
        6. 8.5.3.6 RREG (0010 0rxx)
        7. 8.5.3.7 WREG (0100 00xx dddd dddd)
      4. 8.5.4 Reading Data and Monitoring for New Conversion Results
    6. 8.6 Register Map
      1. 8.6.1 Configuration and Status Registers
      2. 8.6.2 Register Descriptions
        1. 8.6.2.1 Configuration Register (address = 0h) [reset = 00h]
          1. Table 10. Configuration Register Field Descriptions
        2. 8.6.2.2 Status Register (address = 1h) [reset = 00h]
          1. Table 11. Status Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Interface Connections
      2. 9.1.2 Connecting Multiple Devices on the Same I2C Bus
      3. 9.1.3 Unused Inputs and Outputs
      4. 9.1.4 Analog Input Filtering
      5. 9.1.5 External Reference and Ratiometric Measurements
      6. 9.1.6 Establishing Proper Limits on the Absolute Input Voltage
      7. 9.1.7 Pseudo Code Example
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Voltage Monitoring
        2. 9.2.2.2 High-Side Current Measurement
        3. 9.2.2.3 Thermistor Measurement
        4. 9.2.2.4 Register Settings
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Sequencing
    2. 10.2 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.6 I2C Timing Requirements

over operating ambient temperature range and DVDD = 2.3 V to 5.5 V, bus capacitance = 10 pF to 400 pF, and pullup resistor = 1 kΩ (unless otherwise noted)
MIN MAX UNIT
STANDARD-MODE
fSCL SCL clock frequency 0 100 kHz
tHD;STA Hold time, (repeated) START condition.
After this period, the first clock pulse is generated.		 4 µs
tLOW Pulse duration, SCL low 4.7 µs
tHIGH Pulse duration, SCL high 4.0 µs
tSU;STA Setup time, repeated START condition 4.7 µs
tHD;DAT Hold time, data 0 µs
tSU;DAT Setup time, data 250 ns
tr Rise time, SCL, SDA 1000 ns
tf Fall time, SCL, SDA 250 ns
tSU;STO Setup time, STOP condition 4.0 µs
tBUF Bus free time, between STOP and START condition 4.7 µs
tVD;DAT Valid time, data 3.45 µs
tVD;ACK Valid time, acknowledge 3.45 µs
FAST-MODE
fSCL SCL clock frequency 0 400 kHz
tHD;STA Hold time, (repeated) START condition.
After this period, the first clock pulse is generated.		 0.6 µs
tLOW Pulse duration, SCL low 1.3 µs
tHIGH Pulse duration, SCL high 0.6 µs
tSU;STA Setup time, repeated START condition 0.6 µs
tHD;DAT Hold time, data 0 µs
tSU;DAT Setup time, data 100 ns
tr Rise time, SCL, SDA 20 300 ns
tf Fall time, SCL, SDA 20 · (DVDD / 5.5 V) 250 ns
tSU;STO Setup time, STOP condition 0.6 µs
tBUF Bus free time, between STOP and START condition 1.3 µs
tVD;DAT Valid time, data 0.9 µs
tVD;ACK Valid time, acknowledge 0.9 µs
tSP Pulse width of spikes that must be suppressed by the input filter 0 50 ns
FAST-MODE PLUS
fSCL SCL clock frequency 0 1000 kHz
tHD;STA Hold time, (repeated) START condition.
After this period, the first clock pulse is generated.		 0.26 µs
tLOW Pulse duration, SCL low 0.5 µs
tHIGH Pulse duration, SCL high 0.26 µs
tSU;STA Setup time, repeated START condition 0.26 µs
tHD;DAT Hold time, data 0 µs
tSU;DAT Setup time, data 50 ns
tr Rise time, SCL, SDA 120 ns
tf Fall time, SCL, SDA Pullup resistor = 350 Ω 20 · (DVDD / 5.5 V) 120 ns
tSU;STO Setup time, STOP condition 0.26 µs
tBUF Bus free time, between STOP and START condition 0.5 µs
tVD;DAT Valid time, data 0.45 µs
tVD;ACK Valid time, acknowledge 0.45 µs
tSP Pulse duration of spikes that must be suppressed by the input filter 0 50 ns
RESET PIN
tw(RSL) Pulse duration, RESET low 250 ns
td(RSSTA) Delay time, START condition after RESET rising edge(2) 100 ns
DRDY PIN
td(DRSTA) Delay time, START condition after DRDY falling edge 0 ns
TIMEOUT
Timeout(1) 14000 tMOD
(1) See the Timeout section for more information.
tMOD = 1 / fMOD. Modulator frequency fMOD = 256 kHz.
(2) No delay time is required when using the RESET command as long as all I2C timing requirements for the (repeated) START and STOP conditions are met.
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