ZHCSKD9 October 2019 ADS1235-Q1
PRODUCTION DATA.
Figure 82 shows an ac-excited bridge measurement system in the 4-wire, GPIO-control mode. Signal and reference-input filter components are omitted for clarity. The transistors switch the polarity of the excitation voltage provided to the bridge by the drive signals from the ADC GPIO drivers via the spare analog input pins. The timing of the drive signals are synchronized to the ADC conversions. The drive signals are non-overlapping in order to avoid commutation errors that can occur during the switching phase. The resistors located at the gates of each transistor maintain the transistors off at power-on, while the ADC drive signals are initialized by the host after system power up. See Figure 7 for timing of the drive signals.
The recommended configuration sequence for ac-bridge excitation mode follows:
Start the conversions. Adjust the time delay parameter as necessary to provide sufficient bridge switch delay. The delay is based on the time constant of the input and reference filters.