11.1 Layout Guidelines

For best performance, dedicate an entire PCB layer to a ground plane and do not route any other signal traces on this layer. However, depending on restrictions imposed by specific end equipment, a dedicated ground plane may not be practical. If ground plane separation is necessary, make a direct connection of the planes at the ADC. Do not connect individual ground planes at multiple locations because this configuration creates ground loops.

Route digital traces away from the CAPP and CAPN pins and away from all analog inputs and associated components in order to minimize interference.

Avoid long traces on DOUT/DRDY, because high capacitance on this pin can lead to increased ADC noise levels. Use a series resistor or a buffer if long traces are used.

C0G capacitors are preferred for the analog input filters. Evaluate other types of capacitors carefully for input filtering use. Use a C0G-type capacitor for the CAPP to CAPN capacitor. Use X7R-type capacitors for the power supply decoupling capacitors. High-K type capacitors (Y5V) are not recommended. Place the capacitors as close as possible to the device pins using short, direct traces. For optimum performance, use low-impedance connections on the ground-side connections of the bypass capacitors.

When applying an external clock, be sure the clock is free of overshoot and glitches. A source-termination resistor placed at the clock buffer helps control reflections and overshoot. Glitches present on the clock signal can lead to increased noise and possible mis-operation.