ZHCSKD9 October   2019 ADS1235-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      框图
      2.      ADC 转换噪声
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
        1. 8.3.1.1 ESD Diodes
        2. 8.3.1.2 Input Multiplexer
        3. 8.3.1.3 Temperature Sensor
        4. 8.3.1.4 Inputs Open
        5. 8.3.1.5 Internal VCOM Connection
        6. 8.3.1.6 Alternate Functions
      2. 8.3.2 PGA
        1. 8.3.2.1 Input Voltage Range
        2. 8.3.2.2 PGA Bypass Mode
      3. 8.3.3 PGA Voltage Monitor
      4. 8.3.4 Reference Voltage
        1. 8.3.4.1 External Reference
        2. 8.3.4.2 AVDD – AVSS Reference (Default)
        3. 8.3.4.3 Reference Monitor
      5. 8.3.5 General-Purpose Input/Outputs (GPIOs)
      6. 8.3.6 Modulator
      7. 8.3.7 Digital Filter
        1. 8.3.7.1 Sinc Filter
          1. 8.3.7.1.1 Sinc Filter Frequency Response
        2. 8.3.7.2 FIR Filter
          1. 8.3.7.2.1 FIR Filter Frequency Response
        3. 8.3.7.3 Filter Bandwidth
        4. 8.3.7.4 50-Hz and 60-Hz Normal Mode Rejection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Conversion Control
        1. 8.4.1.1 Continuous-Conversion Mode
        2. 8.4.1.2 Pulse-Conversion Mode
        3. 8.4.1.3 Conversion Latency
        4. 8.4.1.4 Start-Conversion Delay
      2. 8.4.2 Chop Mode
      3. 8.4.3 AC-Bridge Excitation Mode
      4. 8.4.4 ADC Clock Mode
      5. 8.4.5 Power-Down Mode
        1. 8.4.5.1 Hardware Power-Down
        2. 8.4.5.2 Software Power-Down
      6. 8.4.6 Reset
        1. 8.4.6.1 Power-on Reset
        2. 8.4.6.2 Reset by Pin
        3. 8.4.6.3 Reset by Command
      7. 8.4.7 Calibration
        1. 8.4.7.1 Offset and Full-Scale Calibration
          1. 8.4.7.1.1 Offset Calibration Registers
          2. 8.4.7.1.2 Full-Scale Calibration Registers
        2. 8.4.7.2 Offset Self-Calibration (SFOCAL)
        3. 8.4.7.3 Offset System-Calibration (SYOCAL)
        4. 8.4.7.4 Full-Scale Calibration (GANCAL)
        5. 8.4.7.5 Calibration Command Procedure
        6. 8.4.7.6 User Calibration Procedure
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Input (DIN)
        4. 8.5.1.4 Data Output/Data Ready (DOUT/DRDY)
        5. 8.5.1.5 Serial Interface Auto-Reset
      2. 8.5.2 Data Ready (DRDY)
        1. 8.5.2.1 DRDY in Continuous-Conversion Mode
        2. 8.5.2.2 DRDY in Pulse-Conversion Mode
        3. 8.5.2.3 Data Ready by Software Polling
      3. 8.5.3 Conversion Data
        1. 8.5.3.1 Status byte (STATUS)
        2. 8.5.3.2 Conversion Data Format
      4. 8.5.4 CRC
      5. 8.5.5 Commands
        1. 8.5.5.1  NOP Command
        2. 8.5.5.2  RESET Command
        3. 8.5.5.3  START Command
        4. 8.5.5.4  STOP Command
        5. 8.5.5.5  RDATA Command
        6. 8.5.5.6  SYOCAL Command
        7. 8.5.5.7  GANCAL Command
        8. 8.5.5.8  SFOCAL Command
        9. 8.5.5.9  RREG Command
        10. 8.5.5.10 WREG Command
        11. 8.5.5.11 LOCK Command
        12. 8.5.5.12 UNLOCK Command
    6. 8.6 Register Map
      1. 8.6.1  Device Identification (ID) Register (address = 00h) [reset = Cxh]
        1. Table 28. ID Register Field Descriptions
      2. 8.6.2  Device Status (STATUS) Register (address = 01h) [reset = 01h]
        1. Table 29. STATUS Register Field Descriptions
      3. 8.6.3  Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
        1. Table 30. MODE0 Register Field Descriptions
      4. 8.6.4  Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
        1. Table 31. MODE1 Register Field Descriptions
      5. 8.6.5  Mode 2 (MODE2) Register (address = 04h) [reset = 00h]
        1. Table 32. MODE2 Register Field Descriptions
      6. 8.6.6  Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
        1. Table 33. MODE3 Register Field Descriptions
      7. 8.6.7  Reference Configuration (REF) Register (address = 06h) [reset = 05h]
        1. Table 34. REF Register Field Descriptions
      8. 8.6.8  Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
        1. Table 35. OFCAL0, OFCAL1, OFCAL2 Registers Field Description
      9. 8.6.9  Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
        1. Table 36. FSCAL0, FSCAL1, FSCAL2 Registers Field Description
      10. 8.6.10 Reserved (RESERVED) Register (address = 0Dh) [reset = FFh]
        1. Table 37. RESERVED Register Field Descriptions
      11. 8.6.11 Reserved (RESERVED) Register (address = 0Eh) [reset = 00h]
        1. Table 38. RESERVED Register Field Descriptions
      12. 8.6.12 Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
        1. Table 39. RESERVED Register Field Descriptions
      13. 8.6.13 PGA Configuration (PGA) Register (address = 10h) [reset = 00h]
        1. Table 40. PGA Register Field Descriptions
      14. 8.6.14 Input Multiplexer (INPMUX) Register (address = 11h) [reset = FFh]
        1. Table 41. INPMUX Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Range
      2. 9.1.2 Input Overload
      3. 9.1.3 Unused Inputs and Outputs
      4. 9.1.4 Multiplexed 2-Bridge Input Example
      5. 9.1.5 AC-Bridge Excitation Example
      6. 9.1.6 Serial Interface and Digital Connections
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Initialization Setup
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Decoupling
    2. 10.2 Analog Power-Supply Clamp
    3. 10.3 Power-Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.1 Noise Performance

The ADS1235-Q1 noise performance depends on the ADC configuration: data rate, PGA gain, digital filter configuration, and chop mode. The combination of the parameters affect noise performance. Two significant factors affecting noise performance are data rate and PGA gain. Since the profile of noise is predominantly white (flat vs frequency), decreasing the data rate proportionally decreases bandwidth and therefore, decreases total noise. Since the noise of the PGA is lower than that of the modulator, increasing the gain decreases overall conversion noise when treated as an input-referred quantity. Noise performance also depends on the digital filter and chop mode. As the order of the digital filter increases, the noise bandwidth correspondingly decreases resulting in decreased noise. Further, as a result of two-point data averaging performed in chop mode, noise decreases by √2 compared to normal operation.

Table 1 shows noise performance in units of μVRMS (RMS = root mean square) and in units of effective resolution (bits) under the conditions listed. The values in parenthesis are peak-to-peak values (µV) and noise free resolution (bits). Noise-free resolution is the resolution of the ADC with no code flicker. The noise-free resolution data are calculated based on the peak-to-peak noise data.

The effective resolution data listed in the tables are calculated using Equation 1:

Equation 1. Effective Resolution or Noise-Free Resolution = ln (FSR / en) / ln (2)

where

  • FSR = full scale range = 2 · VREF / Gain (See Recommended Operating Conditions for limitations of FSR)
  • en = Input referred voltage noise (RMS value to calculate effective resolution, p-p value to calculate noise-free resolution)

The data shown in the noise performance table represent typical ADC performance at TA = 25°C. The noise-performance data are the standard deviation and peak-to-peak computations of the ADC data. The noise data are acquired with inputs shorted, based on consecutive ADC readings for a period of ten seconds or 8192 data points, whichever occurs first. Because of the statistical nature of noise, repeated noise measurements may yield higher or lower noise performance results.

Table 1. Noise in µVRMS (µVPP) and Effective Resolution (Noise-Free Resolution)
at TA = 25°C and VREF = 5 V

DATA RATE FILTER NOISE, µVRMS (µVPP) EFFECTIVE RESOLUTION (Bits), [NOISE-FREE RESOLUTION (Bits)]
GAIN = 1 GAIN = 64 GAIN = 128 GAIN = 1 GAIN = 64 GAIN = 128
2.5 SPS FIR 0.21 (0.6) 0.008 (0.028) 0.011 (0.042) 24 (23.8) 24 (22.4) 22.7 (20.8)
2.5 SPS Sinc1 0.12 (0.3) 0.009 (0.037) 0.008 (0.033) 24 (24) 24 (22) 23.2 (21.2)
2.5 SPS Sinc2 0.15 (0.3) 0.007 (0.023) 0.006 (0.021) 24 (24) 24 (22.7) 23.7 (21.8)
2.5 SPS Sinc3 0.15 (0.3) 0.007 (0.023) 0.005 (0.014) 24 (24) 24 (22.7) 24 (22.4)
2.5 SPS Sinc4 0.15 (0.3) 0.005 (0.019) 0.006 (0.019) 24 (24) 24 (23) 23.7 (22)
5 SPS FIR 0.29 (0.89) 0.013 (0.051) 0.013 (0.051) 24 (23.2) 23.6 (21.5) 22.5 (20.5)
5 SPS Sinc1 0.15 (0.3) 0.015 (0.051) 0.01 (0.044) 24 (24) 23.4 (21.5) 22.9 (20.8)
5 SPS Sinc2 0.17 (0.6) 0.012 (0.047) 0.009 (0.035) 24 (23.8) 23.7 (21.7) 23 (21.1)
5 SPS Sinc3 0.12 (0.6) 0.011 (0.047) 0.008 (0.037) 24 (23.8) 23.7 (21.7) 23.1 (21)
5 SPS Sinc4 0.088 (0.3) 0.007 (0.028) 0.007 (0.03) 24 (24) 24 (22.4) 23.3 (21.3)
10 SPS FIR 0.36 (1.5) 0.022 (0.11) 0.02 (0.096) 24 (22.5) 22.8 (20.5) 21.9 (19.6)
10 SPS Sinc1 0.28 (0.89) 0.015 (0.065) 0.016 (0.082) 24 (23.2) 23.3 (21.2) 22.2 (19.9)
10 SPS Sinc2 0.26 (0.89) 0.015 (0.061) 0.013 (0.065) 24 (23.2) 23.3 (21.3) 22.5 (20.2)
10 SPS Sinc3 0.26 (0.6) 0.014 (0.065) 0.011 (0.047) 24 (23.8) 23.4 (21.2) 22.7 (20.7)
10 SPS Sinc4 0.24 (0.6) 0.013 (0.056) 0.01 (0.042) 24 (23.8) 23.6 (21.4) 22.9 (20.8)
16.6 SPS Sinc1 0.41 (1.8) 0.025 (0.12) 0.022 (0.12) 24 (22.2) 22.6 (20.3) 21.8 (19.4)
16.6 SPS Sinc2 0.32 (1.5) 0.018 (0.089) 0.018 (0.096) 24 (22.5) 23 (20.8) 22 (19.6)
16.6 SPS Sinc3 0.3 (1.2) 0.017 (0.079) 0.018 (0.091) 24 (22.8) 23.1 (20.9) 22.1 (19.7)
16.6 SPS Sinc4 0.23 (1.2) 0.015 (0.084) 0.014 (0.072) 24 (22.8) 23.3 (20.8) 22.4 (20)
20 SPS FIR 0.51 (2.1) 0.032 (0.16) 0.029 (0.16) 24 (22) 22.2 (19.9) 21.3 (18.9)
20 SPS Sinc1 0.44 (2.1) 0.025 (0.13) 0.026 (0.13) 24 (22) 22.6 (20.2) 21.5 (19.2)
20 SPS Sinc2 0.36 (1.2) 0.02 (0.12) 0.02 (0.1) 24 (22.8) 22.9 (20.4) 21.9 (19.5)
20 SPS Sinc3 0.32 (1.5) 0.017 (0.089) 0.018 (0.096) 24 (22.5) 23.1 (20.8) 22 (19.6)
20 SPS Sinc4 0.3 (1.2) 0.017 (0.084) 0.018 (0.1) 24 (22.8) 23.1 (20.8) 22.1 (19.6)
50 SPS Sinc1 0.63 (3.6) 0.04 (0.25) 0.038 (0.23) 23.7 (21.2) 21.9 (19.2) 21 (18.4)
50 SPS Sinc2 0.57 (3) 0.033 (0.21) 0.032 (0.18) 23.9 (21.5) 22.2 (19.5) 21.2 (18.7)
50 SPS Sinc3 0.53 (2.4) 0.03 (0.19) 0.03 (0.17) 24 (21.8) 22.3 (19.7) 21.3 (18.8)
50 SPS Sinc4 0.49 (2.4) 0.028 (0.15) 0.026 (0.16) 24 (21.8) 22.4 (20) 21.5 (18.9)
60 SPS Sinc1 0.71 (3.9) 0.043 (0.27) 0.042 (0.26) 23.6 (21.1) 21.8 (19.1) 20.8 (18.2)
60 SPS Sinc2 0.6 (3.3) 0.036 (0.24) 0.034 (0.21) 23.8 (21.4) 22.1 (19.3) 21.1 (18.5)
60 SPS Sinc3 0.56 (3) 0.032 (0.19) 0.03 (0.17) 23.9 (21.5) 22.2 (19.6) 21.3 (18.8)
60 SPS Sinc4 0.53 (2.7) 0.031 (0.19) 0.03 (0.18) 24 (21.6) 22.3 (19.7) 21.3 (18.7)
100 SPS Sinc1 0.8 (4.8) 0.056 (0.34) 0.054 (0.35) 23.4 (20.8) 21.4 (18.8) 20.5 (17.8)
100 SPS Sinc2 0.68 (4.2) 0.047 (0.29) 0.043 (0.3) 23.6 (21) 21.7 (19) 20.8 (18)
100 SPS Sinc3 0.67 (4.2) 0.042 (0.28) 0.041 (0.27) 23.6 (21) 21.8 (19.1) 20.9 (18.1)
100 SPS Sinc4 0.62 (3.6) 0.039 (0.24) 0.039 (0.27) 23.8 (21.2) 21.9 (19.3) 20.9 (18.2)
400 SPS Sinc1 1.4 (11) 0.11 (0.81) 0.11 (0.75) 22.6 (19.6) 20.4 (17.5) 19.5 (16.7)
400 SPS Sinc2 1.2 (8.3) 0.09 (0.64) 0.086 (0.6) 22.8 (20) 20.7 (17.9) 19.8 (17)
400 SPS Sinc3 1.1 (7.7) 0.082 (0.61) 0.078 (0.56) 22.9 (20.1) 20.9 (18) 19.9 (17.1)
400 SPS Sinc4 1 (7.7) 0.076 (0.59) 0.072 (0.53) 23 (20.1) 21 (18) 20 (17.2)
1200 SPS Sinc1 2.3 (17) 0.18 (1.3) 0.18 (1.4) 21.9 (19) 19.7 (16.9) 18.8 (15.7)
1200 SPS Sinc2 2 (14) 0.15 (1.2) 0.15 (1.1) 22.1 (19.3) 20 (17) 19 (16.1)
1200 SPS Sinc3 1.8 (13) 0.14 (1) 0.13 (1) 22.2 (19.4) 20.1 (17.2) 19.2 (16.2)
1200 SPS Sinc4 1.7 (13) 0.13 (1) 0.13 (0.94) 22.3 (19.4) 20.2 (17.2) 19.2 (16.3)
2400 SPS Sinc1 3.2 (26) 0.25 (2) 0.24 (1.8) 21.4 (18.4) 19.2 (16.2) 18.3 (15.4)
2400 SPS Sinc2 2.7 (20) 0.22 (1.7) 0.21 (1.5) 21.6 (18.7) 19.5 (16.5) 18.5 (15.6)
2400 SPS Sinc3 2.5 (18) 0.2 (1.4) 0.19 (1.4) 21.7 (18.9) 19.6 (16.7) 18.6 (15.8)
2400 SPS Sinc4 2.3 (18) 0.18 (1.5) 0.18 (1.4) 21.8 (18.9) 19.7 (16.7) 18.8 (15.8)
4800 SPS Sinc1 4.4 (35) 0.34 (2.5) 0.32 (2.4) 20.9 (17.9) 18.8 (15.9) 17.9 (15)
4800 SPS Sinc2 3.9 (30) 0.3 (2.3) 0.29 (2.4) 21.1 (18.1) 19 (16.1) 18 (15)
4800 SPS Sinc3 3.6 (27) 0.28 (2) 0.26 (2) 21.2 (18.3) 19.1 (16.3) 18.2 (15.2)
4800 SPS Sinc4 3.4 (27) 0.26 (1.9) 0.25 (1.9) 21.3 (18.3) 19.2 (16.3) 18.2 (15.3)
7200 SPS Sinc1 5.2 (42) 0.38 (2.9) 0.37 (3) 20.7 (17.7) 18.6 (15.7) 17.7 (14.7)
7200 SPS Sinc2 4.7 (37) 0.36 (2.8) 0.34 (2.5) 20.8 (17.9) 18.7 (15.8) 17.8 (14.9)
7200 SPS Sinc3 4.5 (35) 0.34 (2.5) 0.32 (2.4) 20.9 (18) 18.8 (15.9) 17.9 (15)
7200 SPS Sinc4 4.2 (36) 0.32 (2.5) 0.31 (2.3) 21 (17.9) 18.9 (16) 18 (15.1)
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