8.5.1.5 Serial Interface Auto-Reset

The serial interface is reset by taking CS high. Applications that tie CS low do not have the ability to reset the serial interface by CS. If a false SCLK occurs (for example, caused by a noise pulse or clocking glitch), the serial interface may inadvertently advance one or more bit positions, resulting in loss of synchronization to the host. If loss of synchronization occurs, the ADC interface does not respond correctly until the interface is reset.

For applications that tie CS low, the serial interface auto-reset feature recovers the interface in the event that an unintentional SCLK glitch occurs. When the first SCLK low-to-high transition occurs (either caused by a glitch or by normal SCLK activity), seven SCLK transitions must occur within 65536 f_CLK cycles (8.9 ms) to complete the byte transaction, otherwise the serial interface resets. After reset, the interface is ready to begin the next byte transaction. If the byte transaction is completed within the 65536 f_CLK cycles, the serial interface does not reset. The cycle of SCLK detection re-starts at the next rising edge of SCLK. The serial interface is reset by holding SCLK low for a minimum 65536 f_CLK cycles.

The auto-reset function is enabled by the SPITIM bit (default is off). See Figure 3 for timing details.