8.4.2 Chop Mode

The PGA and modulator are chopper-stabilized at high frequency in order to reduce offset voltage, offset voltage drift and 1/f noise. The offset and noise artifacts are modulated to a high frequency by the chop operation, which are removed by the digital filter. Although chopper stabilization is designed to remove all offset, a small offset voltage may remain. The optional global chop mode removes the remaining offset errors, providing near zero offset voltage drift performance.

Chop mode alternates the signal polarity between consecutive conversions in order to remove offset. The ADC subtracts consecutive, alternate-polarity conversions to yield the final conversion data. The result of subtraction removes the offset.

Figure 59. ADC Chop Mode

As shown in Figure 59, the internal chop switch reverses the signal after the input multiplexer. V_OFS models the internal offset voltage. The operational sequence of chop mode is as follows:

Conversion C1: V_AINP – V_AINN – V_OFS → First conversion withheld after start

Conversion C2: V_AINN – V_AINP – V_OFS → Output 1 = (C1 – C2) / 2 = V_AINP – V_AINN

Conversion C3: V_AINP – V_AINN – V_OFS → Output 2 =-(C3 – C2) / 2 = V_AINP – V_AINN

The sequence repeats for all conversions. Because of the required settling time to alternate the internal polarity, the effective data rate in chop mode operation is reduced. The chop mode data rate is proportional to the order of the sinc filter. Referring to Table 6, the new data rate is equal to 1 / latency values; and be aware the chop mode first conversion latency is 2 × latency values. As a consequence of the internal data subtraction, two data points are effectively averaged together. Averaging of data reduces noise by √2. Divide the noise data values shown in Table 1 by √2 to derive the chop mode noise performance data. The null frequencies of the digital filter are not changed in chop-mode operation. However, new null frequencies appear at multiples of f_DATA / 2 as a result of averaging.