米6体育平台手机版

ZHCSFP3C August 2016 – June 2017 ADS124S06 , ADS124S08

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PBS|32
- MPQF027A
RHB|32
- MPQF130D

散热焊盘机械数据 (封装 | 引脚)

PBS|32
- QFND381

订购信息

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

		MIN	MAX	UNIT
Power-supply voltage	AVDD to AVSS	–0.3	5.5	V
	AVSS to DGND	–2.8	0.3
	DVDD to DGND	–0.3	3.9
	IOVDD to DGND	–0.3	5.5
Analog input voltage	AINx, GPIOx, REFPx, REFNx, REFCOM	AVSS – 0.3	AVDD + 0.3	V
Digital input voltage	CS, SCLK, DIN, DOUT/DRDY, DRDY, START, RESET, CLK	DGND – 0.3	IOVDD + 0.3	V
Input current	Continuous, AVSS-SW, REFN0, REFOUT	–100	100	mA
Input current	Continuous, all other pins except power-supply pins	–10	10	mA
Temperature	Junction, T_J		150	°C
Temperature	Storage, T_stg	–60	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2500	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
POWER SUPPLY
	Analog power supply	AVDD to AVSS	2.7		5.25	V
		AVSS to DGND	–2.625	0	0.05
		AVDD to DGND	1.5		5.25
	Digital core power supply	DVDD to DGND	2.7		3.6	V
	Digital IO power supply	IOVDD to DGND	DVDD		5.25	V
ANALOG INPUTS⁽¹⁾
V_(AINx)	Absolute input voltage⁽²⁾	PGA bypassed	AVSS – 0.05		AVDD + 0.05	V
		PGA enabled, gain = 1 to 16	AVSS + 0.15 + \|V_INMAX\|·(Gain – 1) / 2		AVDD – 0.15 – \|V_INMAX\|·(Gain –1) / 2
		PGA enabled, gain = 32 to 128	AVSS + 0.15 + 15.5·\|V_INMAX\|		AVDD – 0.15 – 15.5·\|V_INMAX\|
V_IN	Differential input voltage	V_IN = V_AINP – V_AINN	–V_REF / Gain		V_REF / Gain	V
VOLTAGE REFERENCE INPUTS⁽³⁾
V_REF	Differential reference input voltage	V_REF = V_(REFPx) – V_(REFNx)	0.5		AVDD – AVSS	V
V_(REFNx)	Absolute negative reference voltage	Negative reference buffer disabled	AVSS – 0.05		V_(REFPx) – 0.5	V
V_(REFNx)	Absolute negative reference voltage	Negative reference buffer enabled	AVSS		V_(REFPx) – 0.5	V
V_(REFPx)	Absolute positive reference voltage	Positive reference buffer disabled	V_(REFNx) + 0.5		AVDD + 0.05	V
V_(REFPx)	Absolute positive reference voltage	Positive reference buffer enabled	V_(REFNx) + 0.5		AVDD	V
EXTERNAL CLOCK SOURCE⁽⁴⁾
f_CLK	External clock frequency		2	4.096	4.5	MHz
	Duty cycle		40%	50%	60%
GENERAL-PURPOSE INPUTS (GPIOs)
	Input voltage		AVSS – 0.05		AVDD + 0.05	V
DIGITAL INPUTS (Other than GPIOs)
	Input voltage		DGND		IOVDD	V
TEMPERATURE RANGE
T_A	Operating ambient temperature		–50		125	°C

(1) AIN_P and AIN_N denote the positive and negative inputs of the PGA. Any of the available analog inputs (AINx) can be selected as either AIN_P or AIN_N by the input multiplexer.

(2) V_INMAX denotes the maximum differential input voltage, V_IN, that is expected in the application. |V_INMAX| can be smaller than V_REF / Gain.

(3) REFPx and REFNx denote one of the two available external differential reference input pairs.

(4) An external clock is not required when the internal oscillator is used.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS124S06, ADS124S08		UNIT
		VQFN (RHB)	TQFP (PBS)
		32 PINS	32 PINS
R_θJA	Junction-to-ambient thermal resistance	45.2	75.5	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	28.3	17.1	°C/W
R_θJB	Junction-to-board thermal resistance	15.8	28.5	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	0.4	°C/W
ψ_JB	Junction-to-board characterization parameter	15.7	28.3	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	2.3	n/a	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

minimum and maximum specifications apply from T_A = –50°C to +125°C; Typical specifications are at T_A = 25°C;
all specifications are at AVDD = 2.7 V to 5.25 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, all gains, internal reference, internal oscillator, all data rates, and global chop disabled (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ANALOG INPUTS
	Absolute input current	PGA bypassed, AVSS + 0.1 V ≤ V_(AINx) ≤ AVDD – 0.1 V		0.5		nA
	Absolute input current	PGA enabled, all gains, V_(AINx)MIN ≤ V_(AINx) ≤ V_(AINx)MAX	–2	0.1	2	nA
	Absolute input current drift	PGA bypassed, AVSS + 0.1 V ≤ V_(AINx) ≤ AVDD – 0.1 V		2		pA/°C
	Absolute input current drift	PGA enabled, all gains, V_(AINx)MIN ≤ V_(AINx) ≤ V_(AINx)MAX		2		pA/°C
	Differential input current	PGA bypassed, V_CM = AVDD / 2, –V_REF≤ V_IN ≤ V_REF		1		nA/V
	Differential input current	PGA enabled, all gains, V_CM = AVDD / 2, –V_REF / Gain ≤ V_IN ≤ V_REF / Gain	–1	0.02	1	nA
	Differential input current drift	PGA bypassed, V_CM = AVDD / 2, –V_REF≤ V_IN ≤ V_REF		3		pA/°C
	Differential input current drift	PGA enabled, all gains, V_CM = AVDD / 2, –V_REF / Gain ≤ V_IN ≤ V_REF / Gain		1		pA/°C
PGA
	Gain settings		1, 2, 4, 8, 16, 32, 64, 128
	Startup time	Enabling the PGA in conversion mode		190		µs
SYSTEM PERFORMANCE
	Resolution (no missing codes)		24			Bits
DR	Data rate		2.5, 5, 10, 16.6, 20, 50, 60, 100, 200, 400, 800, 1000, 2000, 4000			SPS
INL	Integral nonlinearity (best fit)	PGA bypassed, V_CM = AVDD / 2		1	10	ppm_FSR
		PGA enabled, gain = 1 to 8, V_CM = AVDD / 2		2	15
		PGA enabled, gain = 16 to 128, V_CM = AVDD / 2, T_A = –40°C to +85°C		3	15
V_IO	Input offset voltage	T_A = 25°C, PGA bypassed	–120	20	120	µV
		T_A = 25°C, PGA enabled, gain = 1 to 8	–120 / Gain	20 / Gain	120 / Gain
		T_A = 25°C, PGA enabled, gain = 16 to 128	–15	2	15
		T_A = 25°C, PGA bypassed, after internal offset calibration	On the order of noise_PP at the set DR and gain
		T_A = 25°C, PGA enabled, gain = 1 to 128, after internal offset calibration	On the order of noise_PP at the set DR and gain
		T_A = 25°C, PGA bypassed, global chop enabled	–2	0.2	2
		T_A = 25°C, PGA enabled, gain = 1 to 128, global chop enabled	–2	0.2	2
	Offset drift	T_A = –40°C to +85°C, PGA bypassed	–75	10	75	nV/°C
		T_A = –40°C to +85°C, PGA enabled, gain = 1 to 128	–100	15	100
		PGA bypassed	–75	10	75
		PGA enabled, gain = 1 to 8	–200	15	200
		PGA enabled, gain = 16 to 128	–150	15	150
		PGA bypassed, global chop enabled	–10	2	10
		PGA enabled, gain = 1 to 128, global chop enabled	–10	2	10
SYSTEM PERFORMANCE (continued)
	Gain error⁽¹⁾	T_A = 25°C, PGA bypassed		40	120	ppm
		T_A = 25°C, PGA enabled, gain = 1 to 32		40	120
		T_A = 25°C, PGA enabled, gain = 64 and 128		40	200
	Gain drift⁽¹⁾	T_A = –40°C to +85°C, PGA bypassed		0.5	1	ppm/°C
		T_A = –40°C to +85°C, PGA enabled, gain = 1 to 128		0.5	2
		PGA bypassed		0.5	1
		PGA enabled, gain = 1 to 128		1	4
	Noise (input-referred)⁽²⁾	PGA enabled, gain = 128, DR = 2.5 SPS, sinc³ filter		19		nV_RMS
NMRR	Normal-mode rejection ratio⁽³⁾	f_IN = 50 Hz or 60 Hz (±1 Hz), DR = 10 SPS, sinc³ filter	88			dB
		f_IN = 50 Hz or 60 Hz (±1 Hz), DR = 10 SPS, sinc³ filter, external f_CLK = 4.096 MHz	102
		f_IN = 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS, low-latency filter	79
		f_IN = 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS, low-latency filter, external f_CLK = 4.096 MHz	95
		f_IN = 50 Hz (±1 Hz), DR = 50 SPS, sinc³ filter	87
		f_IN = 50 Hz (±1 Hz), DR = 50 SPS, sinc³ filter, external f_CLK = 4.096 MHz	101
		f_IN = 60 Hz (±1 Hz), DR = 60 SPS, sinc³ filter	89
		f_IN = 60 Hz (±1 Hz), DR = 60 SPS, sinc³ filter, external f_CLK = 4.096 MHz	105
CMRR	Common-mode rejection ratio	At dc	110	120		dB
		f_CM = 50 Hz or 60 Hz (±1 Hz), DR = 2.5 SPS to 10 SPS, sinc³ filter	120	130
		f_CM = 50 Hz or 60 Hz (±1 Hz), DR = 2.5 SPS, 5 SPS, 10 SPS, 20 SPS, low-latency filter	115	125
PSRR	Power-supply rejection ratio	AVDD at dc	90	105		dB
		AVDD at 50 Hz or 60 Hz	100	115
		DVDD at dc	100	115
VOLTAGE REFERENCE INPUTS
	Absolute input current	Reference buffers disabled, external V_REF = 2.5 V, REFP1/REFN1 inputs	-6	4	6	µA/V
	Absolute input current	Reference buffers enabled, external V_REF = 2.5 V, REFP1/REFN1 inputs	–15	5	15	nA
INTERNAL VOLTAGE REFERENCE
V_REF	Output voltage			2.5		V
	Accuracy	T_A = 25°C, TQFP package	–0.05%	±0.01%	0.05%
	Accuracy	T_A = 25°C, VQFN package	–0.1%	±0.01%	0.1%
	Temperature drift	T_A = –40°C to +85°C		2.5	8	ppm/°C
	Temperature drift	T_A = –50°C to +125°C		3	10	ppm/°C
	Output current	AVDD = 2.7 V to 3.3 V, sink and source	–5		5	mA
	Output current	AVDD = 3.3 V to 5.25 V, sink and source	–10		10	mA
	Short-circuit current limit	Sink and source		70	100	mA
PSRR	Power-supply rejection ratio	AVDD at dc		85		dB
	Load regulation	AVDD = 2.7 V to 3.3 V, load current = –5 mA to 5 mA		8		µV/mA
	Load regulation	AVDD = 3.3 V to 5.25 V, load current = –10 mA to 10 mA		8		µV/mA
	Startup time	1-µF capacitor on REFOUT, 0.001% settling		5.9		ms
	Capacitive load stability	Capacitor on REFOUT	1		47	µF
	Reference noise	f = 0.1 Hz to 10 Hz, 1-µF capacitor on REFOUT		9		µV_PP
INTERNAL OSCILLATOR
f_CLK	Frequency			4.096		MHz
	Accuracy		–1.5%		1.5%
EXCITATION CURRENT SOURCES (IDACS)
	Current settings		10, 50, 100, 250, 500, 750, 1000, 1500, 2000			µA
	Compliance voltage⁽⁴⁾	10 µA to 750 µA, 0.1% deviation	AVSS		AVDD – 0.4	V
	Compliance voltage⁽⁴⁾	1 mA to 2 mA, 0.1% deviation	AVSS		AVDD – 0.6	V
	Accuracy (each IDAC)	T_A = 25°C, 10 µA to 100 µA	–5%	±0.7%	5%
	Accuracy (each IDAC)	T_A = 25°C, 250 µA to 2 mA	–3%	±0.5%	3%
	Current mismatch between IDACs	T_A = 25°C, 10 µA to 100 µA		0.15%	0.8%
		T_A = 25°C, 250 µA to 750 µA		0.10%	0.6%
		T_A = 25°C, 1 mA to 2 mA		0.07%	0.4%
	Temperature drift (each IDAC)	10 µA to 750 µA		20	120	ppm/°C
	Temperature drift (each IDAC)	1 mA to 2 mA		10	80	ppm/°C
	Temperature drift matching between IDACs	10 µA to 100 µA		3	25	ppm/°C
	Temperature drift matching between IDACs	250 µA to 2 mA		2	15	ppm/°C
	Startup time	With internal reference already settled. From end of WREG command to current flowing out of pin.		22		µs
BIAS VOLTAGE
V_BIAS	Output voltage settings		(AVDD + AVSS) / 2, (AVDD + AVSS) / 12			V
	Output impedance			350		Ω
	Startup time	Combined capacitive load on all selected analog inputs C_LOAD = 1 µF, 0.1% settling		2.8		ms
BURNOUT CURRENT SOURCES (BOCS)
	Current settings			0.2, 1, 10		µA
	Accuracy	0.2 µA, sinking or sourcing		±8%
		1 µA, sinking or sourcing		±4%
		10 µA, sinking or sourcing		±2%
PGA RAIL DETECTION
	Positive rail threshold	Referred to the output of the PGA		AVDD – 0.15		V
	Negative rail threshold	Referred to the output of the PGA		AVSS + 0.15		V
REFERENCE DETECTION
	Threshold 1			0.3		V
	Threshold 2		1/3·(AVDD – AVSS)			V
	Threshold 2 accuracy		–3%	±1%	3%
	Pull-together resistance			10		MΩ
SUPPLY VOLTAGE MONITORS
	Accuracy	(AVDD – AVSS) / 4 monitor		±1%
	Accuracy	DVDD / 4 monitor		±1%
TEMPERATURE SENSOR
	Output voltage	T_A = 25°C		129		mV
	Temperature coefficient			403		µV/°C
LOW-SIDE POWER SWITCH
R_ON	On-resistance			1	3	Ω
	Current through switch				75	mA
GENERAL-PURPOSE INPUT/OUTPUTS (GPIOs)
V_IL	Logic input level, low		AVSS – 0.05		0.3 AVDD	V
V_IH	Logic input level, high		0.7 AVDD		AVDD + 0.05	V
V_OL	Logic output level, low	I_OL = 1 mA	AVSS		0.2 AVDD	V
V_OH	Logic output level, high	I_OH = 1 mA	0.8 AVDD		AVDD	V
DIGITAL INPUT/OUTPUTS
V_IL	Logic input level, low		DGND		0.3 IOVDD	V
V_IH	Logic input level, high		0.7 IOVDD		IOVDD	V
V_OL	Logic output level, low	I_OL = 1 mA	DGND		0.2 IOVDD	V
V_OH	Logic output level, high	I_OH = 1 mA	0.8 IOVDD		IOVDD	V
	Input current	DGND ≤ V_{Digital Input} ≤ IOVDD	–1		1	µA
ANALOG SUPPLY CURRENT (AVDD = 3.3 V, External Reference, Internal Reference Disabled, Reference Buffers Disabled, IDACs Disabled, VBIAS Disabled, Flags Disabled, Internal Oscillator, All Data Rates, V_IN = 0 V)
I_AVDD	Analog supply current	Power-down mode		0.1	1.5	µA
		Standby mode, PGA bypassed		70
		Conversion mode, PGA bypassed		85
		Conversion mode, PGA enabled, gain = 1, 2		120	135
		Conversion mode, PGA enabled, gain = 4, 8		140	155
		Conversion mode, PGA enabled, gain = 16, 32		165	180
		Conversion mode, PGA enabled, gain = 64		200
		Conversion mode, PGA enabled, gain = 128		250
ADDITIONAL ANALOG SUPPLY CURRENTS PER FUNCTION (AVDD = 3.3 V)
I_AVDD	Analog supply current	Internal 2.5-V reference, no external load		185	280	µA
		Positive reference buffer		35	60
		Negative reference buffer		25	40
		VBIAS buffer, no external load		10
		IDAC overhead, 10 µA to 250 µA		20	35
		IDAC overhead, 500 µA to 750 µA		30
		IDAC overhead, 1 mA		40
		IDAC overhead, 1.5 mA		50
		IDAC overhead, 2 mA		65
		PGA rail detection and reference detection circuit		10
DIGITAL SUPPLY CURRENT (DVDD = IOVDD = 3.3 V, All Data Rates, SPI Not Active)
I_DVDD + I_IOVDD	Digital supply current	Power-down mode, internal oscillator		0.1		µA
		Standby mode, internal oscillator		185
		Conversion mode, internal oscillator		225	300
		Conversion mode, external f_CLK = 4.096 MHz		195
POWER DISSIPATION (AVDD = DVDD = IOVDD = 3.3 V, Internal Reference Enabled, Reference Buffers Disabled, IDACs Disabled, VBIAS Disabled, Flags Disabled, Internal Oscillator, All Data Rates, V_IN = 0 V, SPI Not Active)
P_D	Power dissipation	Conversion mode, PGA enabled, gain = 1		1.75		mW

(1) Excluding error of voltage reference.

(2) See the Noise Performance section for more information.

(3) See the 50-Hz and 60-Hz Line Cycle Rejection section for more information.

(4) The IDAC current does not change by more than 0.1% from the nominal value when staying within the specified compliance voltage.

7.6 Timing Characteristics

over operating ambient temperature range, DVDD = 2.7 V to 3.6 V, IOVDD = DVDD to 5.25 V, and
DOUT/DRDY load = 20 pF || 100 kΩ to DGND (unless otherwise noted)

		MIN	UNIT⁽¹⁾
SERIAL INTERFACE
t_d(CSSC)	Delay time, first SCLK rising edge after CS falling edge	20	ns
t_d(SCCS)	Delay time, CS rising edge after final SCLK falling edge	20	ns
t_w(CSH)	Pulse duration, CS high	30	ns
t_c(SC)	SCLK period	100	ns
t_w(SCH)	Pulse duration, SCLK high	40	ns
t_w(SCL)	Pulse duration, SCLK low	40	ns
t_su(DI)	Setup time, DIN valid before SCLK falling edge	15	ns
t_h(DI)	Hold time, DIN valid after SCLK falling edge	20	ns
t_d(CMD)	Delay time, between bytes or commands	0	ns
RESET PIN
t_w(RSL)	Pulse duration, RESET low	4	t_CLK
t_d(RSSC)	Delay time, first SCLK rising edge after RESET rising edge (or 7th SCLK falling edge of RESET command)	4096	t_CLK
START/SYNC PIN
t_w(STH)	Pulse duration, START/SYNC high	4	t_CLK
t_w(STL)	Pulse duration, START/SYNC low	4	t_CLK
t_su(STDR)	Setup time, START/SYNC falling edge (or 7th SCLK falling edge of STOP command) before DRDY falling edge to stop further conversions (continuous conversion mode)	32	t_CLK
READING CONVERSION DATA WITHOUT RDATA COMMAND
t_h(SCDR)	Hold time, SCLK low before DRDY falling edge⁽²⁾	28	t_CLK
t_d(DRSC)	Delay time, SCLK rising edge after DRDY falling edge⁽²⁾	4	t_CLK

(1) t_CLK = 1 / f_CLK.

(2) Only applicable when reading data without the RDATA command. All commands can be send without any SCLK to DRDY signal timing restrictions.

7.7 Switching Characteristics

over operating ambient temperature range, DVDD = 2.7 V to 3.6 V, IOVDD = DVDD to 5.25 V, and
DOUT/DRDY load = 20 pF || 100 kΩ to DGND (unless otherwise noted)

PARAMETER		MIN	MAX	UNIT⁽¹⁾
t_p(CSDO)	Propagation delay time, CS falling edge to DOUT driven	0	25	ns
t_p(SCDO)	Propagation delay time, SCLK rising edge to valid new DOUT	3	30	ns
t_p(CSDOZ)	Propagation delay time, CS rising edge to DOUT high impedance	0	25	ns
t_p(STDR)	Propagation delay time, START/SYNC rising edge (or first SCLK rising edge of any command or data read) to DRDY rising edge		2	t_CLK
t_w(DRH)	Pulse duration, DRDY high	24		t_CLK
t_p(GPIO)	Propagation delay time, last SCLK falling edge of WREG command to GPIOx output valid	3	100	ns
	SPI timeout per 8 bit⁽²⁾	2¹⁵		t_CLK

(1) t_CLK = 1 / f_CLK

(2) The SPI interface resets when an entire byte is not sent within the specified timeout time.

NOTE:

Single-byte communication is shown. Actual communication can be multiple bytes.

Figure 1. Serial Interface Timing Requirements

NOTE:

Single-byte communication is shown. Actual communication can be multiple bytes.

Figure 2. Serial Interface Switching Characteristics

ADS124S06 ADS124S08 ai_reset_timing_sbas660.gif

Figure 3. RESET Pin and RESET Command Timing Requirements

ADS124S06 ADS124S08 ai_start_pin_timing_sbas660.gif

Figure 4. START/SYNC Pin Timing Requirements

ADS124S06 ADS124S08 ai_start_command_timing_sbas660.gif

Figure 5. START Command Timing Requirements

ADS124S06 ADS124S08 ai_rd_data_drct_tim_sbas660.gif

Figure 6. Read Data Direct (Without an RDATA Command) Timing Requirements

ADS124S06 ADS124S08 ai_gpio_timing_sbas660.gif

Figure 7. GPIO Switching Characteristics

7.8 Typical Characteristics

at T_A = 25°C, AVDD = 3.3 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, using internal V_REF = 2.5 V, internal 4.096-MHz oscillator, and PGA enabled (unless otherwise noted)

PGA bypassed, DR = 20 SPS, V_IN = 0 V

Figure 8. Absolute Input Current vs Absolute Input Voltage

PGA enabled, gain = 1, DR = 20 SPS, V_IN = 0 V

Figure 10. Absolute Input Current vs Absolute Input Voltage

PGA bypassed, DR = 20 SPS, V_CM = 1.65 V

Figure 12. Differential Input Current vs Differential Input Voltage

PGA enabled, DR = 20 SPS, V_CM = 1.65 V

Figure 14. Differential Input Current vs Differential Input Voltage

PGA bypassed, gain = 1

Figure 16. INL vs Differential Input Voltage

Figure 18. INL vs Temperature

Figure 20. Gain Error vs Temperature

Figure 22. Internal Reference Voltage vs AVDD

Figure 24. Internal Oscillator Frequency Histogram

Figure 26. IDAC Accuracy vs Compliance Voltage

IDAC output voltage = 1.65 V

Figure 28. IDAC Accuracy vs Temperature

Figure 30. VBIAS Voltage [(AVDD – AVSS) / 2] vs Temperature

Figure 32. PGA Rail Detection, PGAN_RAILP, PGAP_RAILP Threshold From AVDD

Level 0 = 300 mV

Figure 34. Reference Threshold Voltage, Level 0

Figure 36. Temperature Sensor Voltage vs Temperature

AVDD = 3.3 V

Figure 38. GPIO Pin Output Voltage vs Sourcing Current

DVDD = 3.3 V

Figure 40. Digital Pin Output Voltage vs Sourcing Current

Standby and conversion mode, external V_REF

Figure 42. Analog Supply Current vs Temperature

Power-down mode

Figure 44. Analog Supply Current vs Temperature

Standby and conversion mode

Figure 46. Digital Supply Current vs Temperature

Power-down mode

Figure 48. Digital Supply Current vs Temperature

PGA bypassed, DR = 4 kSPS, V_IN = 0 V

Figure 9. Absolute Input Current vs Absolute Input Voltage

PGA enabled, gain = 1, DR = 4 kSPS, V_IN = 0 V

Figure 11. Absolute Input Current vs Absolute Input Voltage

PGA bypassed, DR = 4 kSPS, V_CM = 1.65 V

Figure 13. Differential Input Current vs Differential Input Voltage

PGA enabled, DR = 4 kSPS, V_CM = 1.65 V

Figure 15. Differential Input Current vs Differential Input Voltage

PGA enabled, gain = 1

Figure 17. INL vs Differential Input Voltage

Figure 19. Offset Voltage vs Temperature

28 units, TQFP package

Figure 21. Internal Reference Voltage vs Temperature

Figure 23. Internal Reference Voltage Noise

	28 units

Figure 25. Internal Oscillator Frequency vs Temperature

Figure 27. IDAC Accuracy vs Compliance Voltage

Figure 29. IDAC Matching vs Temperature

Figure 31. VBIAS Voltage [(AVDD – AVSS) / 12] vs Temperature

Figure 33. PGA Rail Detection, PGAN_RAILN, PGAP_RAILN Threshold From AVSS

Level 1 = 1/3 · (AVDD – AVSS)

Figure 35. Reference Threshold Voltage, Level 1

Figure 37. Low-Side Switch R_ON vs Temperature

AVDD = 3.3 V

Figure 39. GPIO Pin Output Voltage vs Sinking Current

DVDD = 3.3 V

Figure 41. Digital Pin Output Voltage vs Sinking Current

Conversion mode, external V_REF

Figure 43. Analog Supply Current vs AVDD

Figure 45. Internal Reference AVDD Current vs Temperature

Conversion mode

Figure 47. Digital Supply Current vs DVDD