ZHCSEA6B
September 2015 – April 2016
ADS1257
PRODUCTION DATA.
1
特性
2
应用
3
说明
4
修订历史记录
5
Device Comparison Table
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Serial Interface Timing Requirements
7.7
Serial Interface Switching Characteristics
7.8
RESET and SYNC/PWDN Timing Requirements
7.9
SCLK Reset Timing Requirements
7.10
DRDY Update Timing Characteristics
7.11
Typical Characteristics
8
Parameter Measurement Information
8.1
Noise Performance
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Input Multiplexer
9.3.2
Analog Input Buffer
9.3.3
Programmable Gain Amplifier (PGA)
9.3.4
Modulator Input Circuitry
9.3.5
Voltage Reference Inputs (REFP, REFN)
9.3.6
Clock Input (CLKIN)
9.3.7
Clock Output (D0/CLKOUT)
9.3.8
General-Purpose Digital I/O (D0, D1)
9.3.9
Open- and Short-Circuit Sensor Detection
9.3.10
Digital Filter
9.3.10.1
Frequency Response
9.3.10.2
50-Hz and 60-Hz, Line Cycle Rejection
9.3.10.3
Settling Time
9.4
Device Functional Modes
9.4.1
Power-Up
9.4.2
Reset
9.4.3
Standby Mode
9.4.4
Power-Down Mode
9.4.5
Conversion Control and Synchronization
9.4.5.1
Settling Time Using Synchronization
9.4.5.2
Settling Time Using Single-Shot Mode
9.4.5.3
Settling Time Using the Input Multiplexer
9.4.5.4
Settling Time while Continuously Converting
9.4.6
Calibration
9.4.6.1
Self-Calibration
9.4.6.1.1
SELFOCAL Command: Self-Offset Calibration
9.4.6.1.2
SELFGCAL Command: Self-Gain Calibration
9.4.6.1.3
SELFCAL Command: Self-Offset and Self-Gain Calibration
9.4.6.2
System Calibration
9.4.6.2.1
SYSOCAL Command: System-Offset Calibration
9.4.6.2.2
SYSGCAL Command: System-Gain Calibration
9.4.6.3
Auto-Calibration
9.5
Programming
9.5.1
Serial Interface
9.5.1.1
Chip Select (CS)
9.5.1.2
Serial Clock (SCLK)
9.5.1.3
Data Input (DIN) and Data Output (DOUT)
9.5.1.4
Data Ready (DRDY)
9.5.2
Data Format
9.5.3
Command Definitions
9.5.3.1
WAKEUP/NOP: Complete Synchronization or Exit Standby Mode
9.5.3.2
RDATA: Read Data
9.5.3.3
RDATAC: Read Data Continuous
9.5.3.4
SDATAC: Stop Read Data Continuous
9.5.3.5
RREG: Read from Registers
9.5.3.6
WREG: Write to Register
9.5.3.7
SELFCAL: Self-Offset and Self-Gain Calibration
9.5.3.8
SELFOCAL: Self Offset Calibration
9.5.3.9
SELFGCAL: Self Gain Calibration
9.5.3.10
SYSOCAL: System Offset Calibration
9.5.3.11
SYSGCAL: System Gain Calibration
9.5.3.12
STANDBY: Standby Mode / Single-shot Mode
9.5.3.13
RESET: Reset Registers to Default Values
9.5.3.14
SYNC: Synchronize the Analog-to-Digital Conversion
9.6
Register Map
9.6.1
STATUS: Status Register (address = 00h) [reset = x1h]
9.6.2
MUX : Input Multiplexer Control Register (address = 01h) [reset = 01h]
9.6.3
ADCON: ADC Control Register (address = 02h) [reset = 20h]
9.6.4
DRATE: ADC Data Rate Register (address = 03h) [reset = F0h]
9.6.5
IO: GPIO Control Register (address = 04h) [reset = E0h]
9.6.6
OFC0: Offset Calibration Register 0 (address = 05h) [reset = depends on calibration results]
9.6.7
OFC1: Offset Calibration Register 1 (address = 06h) [reset = depends on calibration results]
9.6.8
OFC2: Offset Calibration Register 2 (address = 07h) [reset = depends on calibration results]
9.6.9
FSC0: Full-Scale Calibration Register 0 (address = 08h) [reset = depends on calibration results]
9.6.10
FSC1: Full-Scale Calibration Register 1 (address = 09h) [reset = depends on calibration results]
9.6.11
FSC2: Full-Scale Calibration Register 2 (address = 0Ah) [reset = depends on calibration results]
10
Applications and Implementation
10.1
Application Information
10.1.1
Basic Connections
10.1.2
Digital Interface Connections
10.1.3
Analog Input Filtering
10.1.4
External Reference
10.1.5
Isolated (or Floating) Sensor Inputs
10.1.6
Unused Inputs and Outputs
10.1.7
Pseudo Code Example
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
Detailed Design Procedure for ±10-V Input
10.2.2.1.1
Absolute Input Voltage Range
10.2.2.1.2
Differential Input Voltage Range
10.2.2.1.3
Level-Shifted Resistor Divider Sizing
10.2.2.1.4
Input Filtering
10.2.2.1.5
Register Settings for ±10-V Input
10.2.2.1.6
Voltage Input Design Variations
10.2.2.2
Detailed Design Procedure for 4-mA to 20-mA Input
10.2.2.2.1
PGA Gain Selection
10.2.2.2.2
Current-Sense Resistor Sizing
10.2.2.2.3
Register Settings for 4-mA to 20-mA Input
10.2.2.2.4
Current Input Design Variations
10.2.3
Application Curves
10.3
Dos and Don'ts
11
Power Supply Recommendations
11.1
Power-Supply Sequencing
11.2
Power-Supply Decoupling
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
器件和文档支持
13.1
文档支持
13.1.1
相关文档
13.2
社区资源
13.3
商标
13.4
静电放电警告
13.5
Glossary
14
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
RGW|20
MPQF122C
散热焊盘机械数据 (封装 | 引脚)
RGW|20
QFND012L
订购信息
zhcsea6b_oa
zhcsea6b_pm
5 Device Comparison Table
DEVICE
SINGLE-ENDED INPUTS
DIFFERENTIAL INPUTS
NUMBER OF GPIOS
ADS1255
2
1
2
ADS1256
8
4
4
ADS1257
3
2
2
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