ZHCSEA6B September   2015  – April 2016 ADS1257

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Serial Interface Timing Requirements
    7. 7.7  Serial Interface Switching Characteristics
    8. 7.8  RESET and SYNC/PWDN Timing Requirements
    9. 7.9  SCLK Reset Timing Requirements
    10. 7.10 DRDY Update Timing Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Input Multiplexer
      2. 9.3.2  Analog Input Buffer
      3. 9.3.3  Programmable Gain Amplifier (PGA)
      4. 9.3.4  Modulator Input Circuitry
      5. 9.3.5  Voltage Reference Inputs (REFP, REFN)
      6. 9.3.6  Clock Input (CLKIN)
      7. 9.3.7  Clock Output (D0/CLKOUT)
      8. 9.3.8  General-Purpose Digital I/O (D0, D1)
      9. 9.3.9  Open- and Short-Circuit Sensor Detection
      10. 9.3.10 Digital Filter
        1. 9.3.10.1 Frequency Response
        2. 9.3.10.2 50-Hz and 60-Hz, Line Cycle Rejection
        3. 9.3.10.3 Settling Time
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Up
      2. 9.4.2 Reset
      3. 9.4.3 Standby Mode
      4. 9.4.4 Power-Down Mode
      5. 9.4.5 Conversion Control and Synchronization
        1. 9.4.5.1 Settling Time Using Synchronization
        2. 9.4.5.2 Settling Time Using Single-Shot Mode
        3. 9.4.5.3 Settling Time Using the Input Multiplexer
        4. 9.4.5.4 Settling Time while Continuously Converting
      6. 9.4.6 Calibration
        1. 9.4.6.1 Self-Calibration
          1. 9.4.6.1.1 SELFOCAL Command: Self-Offset Calibration
          2. 9.4.6.1.2 SELFGCAL Command: Self-Gain Calibration
          3. 9.4.6.1.3 SELFCAL Command: Self-Offset and Self-Gain Calibration
        2. 9.4.6.2 System Calibration
          1. 9.4.6.2.1 SYSOCAL Command: System-Offset Calibration
          2. 9.4.6.2.2 SYSGCAL Command: System-Gain Calibration
        3. 9.4.6.3 Auto-Calibration
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN) and Data Output (DOUT)
        4. 9.5.1.4 Data Ready (DRDY)
      2. 9.5.2 Data Format
      3. 9.5.3 Command Definitions
        1. 9.5.3.1  WAKEUP/NOP: Complete Synchronization or Exit Standby Mode
        2. 9.5.3.2  RDATA: Read Data
        3. 9.5.3.3  RDATAC: Read Data Continuous
        4. 9.5.3.4  SDATAC: Stop Read Data Continuous
        5. 9.5.3.5  RREG: Read from Registers
        6. 9.5.3.6  WREG: Write to Register
        7. 9.5.3.7  SELFCAL: Self-Offset and Self-Gain Calibration
        8. 9.5.3.8  SELFOCAL: Self Offset Calibration
        9. 9.5.3.9  SELFGCAL: Self Gain Calibration
        10. 9.5.3.10 SYSOCAL: System Offset Calibration
        11. 9.5.3.11 SYSGCAL: System Gain Calibration
        12. 9.5.3.12 STANDBY: Standby Mode / Single-shot Mode
        13. 9.5.3.13 RESET: Reset Registers to Default Values
        14. 9.5.3.14 SYNC: Synchronize the Analog-to-Digital Conversion
    6. 9.6 Register Map
      1. 9.6.1  STATUS: Status Register (address = 00h) [reset = x1h]
      2. 9.6.2  MUX : Input Multiplexer Control Register (address = 01h) [reset = 01h]
      3. 9.6.3  ADCON: ADC Control Register (address = 02h) [reset = 20h]
      4. 9.6.4  DRATE: ADC Data Rate Register (address = 03h) [reset = F0h]
      5. 9.6.5  IO: GPIO Control Register (address = 04h) [reset = E0h]
      6. 9.6.6  OFC0: Offset Calibration Register 0 (address = 05h) [reset = depends on calibration results]
      7. 9.6.7  OFC1: Offset Calibration Register 1 (address = 06h) [reset = depends on calibration results]
      8. 9.6.8  OFC2: Offset Calibration Register 2 (address = 07h) [reset = depends on calibration results]
      9. 9.6.9  FSC0: Full-Scale Calibration Register 0 (address = 08h) [reset = depends on calibration results]
      10. 9.6.10 FSC1: Full-Scale Calibration Register 1 (address = 09h) [reset = depends on calibration results]
      11. 9.6.11 FSC2: Full-Scale Calibration Register 2 (address = 0Ah) [reset = depends on calibration results]
  10. 10Applications and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Basic Connections
      2. 10.1.2 Digital Interface Connections
      3. 10.1.3 Analog Input Filtering
      4. 10.1.4 External Reference
      5. 10.1.5 Isolated (or Floating) Sensor Inputs
      6. 10.1.6 Unused Inputs and Outputs
      7. 10.1.7 Pseudo Code Example
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Detailed Design Procedure for ±10-V Input
          1. 10.2.2.1.1 Absolute Input Voltage Range
          2. 10.2.2.1.2 Differential Input Voltage Range
          3. 10.2.2.1.3 Level-Shifted Resistor Divider Sizing
          4. 10.2.2.1.4 Input Filtering
          5. 10.2.2.1.5 Register Settings for ±10-V Input
          6. 10.2.2.1.6 Voltage Input Design Variations
        2. 10.2.2.2 Detailed Design Procedure for 4-mA to 20-mA Input
          1. 10.2.2.2.1 PGA Gain Selection
          2. 10.2.2.2.2 Current-Sense Resistor Sizing
          3. 10.2.2.2.3 Register Settings for 4-mA to 20-mA Input
          4. 10.2.2.2.4 Current Input Design Variations
      3. 10.2.3 Application Curves
    3. 10.3 Dos and Don'ts
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Sequencing
    2. 11.2 Power-Supply Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 Glossary
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Parameter Measurement Information

8.1 Noise Performance

The ADS1257 offers outstanding noise performance that can be optimized by adjusting the data rate or PGA gain setting. As the averaging is increased by reducing the data rate, the noise drops correspondingly. The PGA reduces the input-referred noise when measuring lower level signals. Table 1 through Table 4 summarize the typical noise performance with the inputs shorted externally.

In all four tables, the following conditions apply: TA = 25°C, AVDD = 5 V, DVDD = 1.8 V, VREF = 2.5 V, and f(CLKIN) = 7.68 MHz.

Table 1 and Table 3 show the root-mean-square (RMS) value of the input-referred noise. Table 2 and Table 4 show the effective number of bits of resolution (ENOB), using the noise data from Table 1 and Table 3 respectively. ENOB is defined as shown in Equation 1:

Equation 1. ADS1257 eq1_enob_sbas288.gif

where

Table 2 and Table 4 also show the noise-free bits of resolution in parenthesis. Noise-free bits are calculated with the same formula as ENOB except the peak-to-peak noise values are used instead of RMS noise.

Table 1. Input-Referred Noise (μVRMS) With Buffer On

DATA RATE
(SPS)		 PGA GAIN
1 2 4 8 16 32 64
2.5 0.247 0.156 0.080 0.056 0.043 0.037 0.033
5 0.301 0.175 0.102 0.076 0.061 0.045 0.044
10 0.339 0.214 0.138 0.106 0.082 0.061 0.061
15 0.401 0.264 0.169 0.126 0.107 0.085 0.073
25 0.494 0.305 0.224 0.149 0.134 0.102 0.093
30 0.533 0.335 0.245 0.176 0.138 0.104 0.106
50 0.629 0.393 0.292 0.216 0.168 0.136 0.122
60 0.692 0.438 0.321 0.233 0.184 0.146 0.131
100 0.875 0.589 0.409 0.305 0.229 0.170 0.169
500 1.946 1.250 0.630 0.648 0.497 0.390 0.367
1000 2.931 1.891 1.325 1.070 0.689 0.512 0.486
2000 4.173 2.589 1.827 1.492 0.943 0.692 0.654
3750 5.394 3.460 2.376 1.865 1.224 0.912 0.906
7500 7.249 4.593 3.149 2.436 1.691 1.234 1.187
15,000 9.074 5.921 3.961 2.984 2.125 1.517 1.515
30,000 10.728 6.705 4.446 3.280 2.416 1.785 1.742

Table 2. Effective Number of Bits (Noise-Free Resolution) With Buffer On

DATA RATE
(SPS)		 PGA GAIN
1(1) 2 4 8 16 32 64
2.5 24.5 (22.3) 24.9 (22.6) 24.9 (22.1) 24.4 (21.7) 23.8 (21.3) 23.0 (20.8) 22.2 (19.7)
5 24.2 (21.6) 24.8 (22.4) 24.5 (21.9) 24.0 (21.3) 23.3 (20.7) 22.7 (20.3) 21.8 (19.3)
10 24.1 (21.6) 24.5 (22.0) 24.1 (21.6) 23.5 (21.0) 22.9 (20.4) 22.3 (19.9) 21.3 (18.9)
15 23.8 (21.3) 24.2 (21.7) 23.8 (21.3) 23.2 (20.7) 22.5 (20.1) 21.8 (19.3) 21.0 (18.7)
25 23.5 (21.0) 24.0 (21.4) 23.4 (21.1) 23.0 (20.5) 22.2 (19.7) 21.5 (19.2) 20.7 (18.5)
30 23.4 (21.1) 23.8 (21.3) 23.3 (20.8) 22.8 (20.4) 22.1 (19.8) 21.5 (19.0) 20.5 (18.1)
50 23.2 (20.6) 23.6 (21.1) 23.0 (20.4) 22.5 (19.9) 21.8 (19.4) 21.1 (18.8) 20.3 (17.9)
60 23.0 (20.6) 23.4 (20.9) 22.9 (20.5) 22.4 (19.8) 21.7 (19.3) 21.0 (18.8) 20.2 (17.8)
100 22.7 (20.2) 23.0 (20.7) 22.5 (20.2) 22.0 (19.6) 21.4 (19.1) 20.8 (18.5) 19.8 (17.4)
500 21.6 (19.4) 21.9 (19.6) 21.5 (19.1) 20.9 (18.6) 20.3 (18.0) 19.6 (17.3) 18.7 (16.3)
1000 21.0 (18.3) 21.3 (18.6) 20.8 (18.1) 20.2 (17.5) 19.8 (17.2) 19.2 (16.5) 18.3 (15.6)
2000 20.5 (17.8) 20.9 (18.1) 20.4 (17.8) 19.7 (17.0) 19.3 (16.6) 18.8 (16.1) 17.9 (15.3)
3750 20.1 (17.4) 20.5 (17.8) 20.0 (17.3) 19.4 (16.6) 19.0 (16.2) 18.4 (15.7) 17.4 (14.7)
7500 19.7 (17.0) 20.1 (17.3) 19.6 (16.9) 19.0 (16.2) 18.5 (15.8) 17.9 (15.3) 17.0 (14.4)
15,000 19.3 (16.6) 19.7 (17.0) 19.3 (16.5) 18.7 (15.9) 18.2 (15.5) 17.7 (14.9) 16.7 (13.9)
30,000 19.1 (16.4) 19.5 (16.7) 19.1 (16.4) 18.5 (15.9) 18.0 (15.4) 17.4 (14.6) 16.5 (13.8)
(1) The full FSR cannot be used when VREF = 2.5 V, gain = 1 V/V, and buffer enabled because of the limited absolute input voltage. Therefore, the values in this column are calculated using a maximum FSR = 6 V.

Table 3. Input-Referred Noise (μVRMS) With Buffer Off

DATA RATE
(SPS)		 PGA GAIN
1 2 4 8 16 32 64
2.5 0.247 0.149 0.097 0.058 0.036 0.031 0.027
5 0.275 0.176 0.109 0.07 0.046 0.039 0.038
10 0.338 0.201 0.129 0.084 0.063 0.048 0.047
15 0.401 0.221 0.15 0.109 0.07 0.063 0.057
25 0.485 0.279 0.177 0.136 0.093 0.076 0.076
30 0.559 0.315 0.202 0.142 0.107 0.093 0.082
50 0.644 0.39 0.238 0.187 0.129 0.108 0.103
60 0.688 0.417 0.281 0.204 0.134 0.109 0.111
100 0.815 0.53 0.36 0.233 0.169 0.123 0.122
500 1.957 1.148 0.772 0.531 0.375 0.276 0.259
1000 2.803 1.797 1.191 0.94 0.518 0.392 0.365
2000 4.025 2.444 1.615 1.31 0.7 0.526 0.461
3750 5.413 3.25 2.061 1.578 0.914 0.693 0.625
7500 7.017 4.143 2.722 1.998 1.241 0.914 0.857
15,000 8.862 5.432 3.378 2.411 1.569 1.149 1.051
30,000 10.341 6.137 3.873 2.775 1.805 1.313 1.211

Table 4. Effective Number of Bits (Noise-Free Resolution) With Buffer Off

DATA RATE
(SPS)		 PGA GAIN
1 2 4 8 16 32 64
2.5 25.3 (23.0) 25.0 (22.4) 24.6 (22.0) 24.4 (21.9) 24.0 (21.3) 23.2 (21.1) 22.5 (20.0)
5 25.1 (22.4) 24.8 (22.1) 24.5 (21.9) 24.1 (21.5) 23.7 (21.2) 22.9 (20.4) 22.0 (19.4)
10 24.8 (22.3) 24.6 (22.1) 24.2 (21.7) 23.8 (21.5) 23.2 (20.8) 22.6 (20.3) 21.7 (19.2)
15 24.6 (22.0) 24.4 (21.8) 24.0 (21.4) 23.4 (20.8) 23.1 (20.6) 22.2 (19.9) 21.4 (19.0)
25 24.3 (21.8) 24.1 (21.7) 23.8 (21.1) 23.1 (20.7) 22.7 (20.3) 22.0 (19.5) 21.0 (18.6)
30 24.1 (21.6) 23.9 (21.4) 23.6 (21.1) 23.1 (20.4) 22.5 (20.0) 21.7 (16.4) 20.9 (18.5)
50 23.9 (21.3) 23.6 (21.3) 23.3 (20.7) 22.7 (20.1) 22.2 (19.8) 21.5 (19.1) 20.5 (18.2)
60 23.8 (21.2) 23.5 (21.0) 23.1 (20.6) 22.5 (20.0) 22.1 (19.8) 21.5 (19.1) 20.4 (18.1)
100 23.5 (21.1) 23.2 (20.5) 22.7 (20.3) 22.4 (19.9) 21.8 (19.5) 21.3 (19.0) 20.3 (17.9)
500 22.3 (20.0) 22.1 (19.7) 21.6 (19.3) 21.2 (18.9) 20.7 (18.3) 20.1 (17.8) 19.2 (16.9)
1000 21.8 (19.0) 21.4 (18.7) 21.0 (18.4) 20.3 (17.7) 20.2 (17.5) 19.6 (16.9) 18.7 (15.9)
2000 21.2 (18.5) 21.0 (18.3) 20.6 (17.9) 19.9 (17.4) 19.8 (17.0) 19.2 (16.4) 18.4 (15.6)
3750 20.8 (18.1) 20.6 (17.8) 20.2 (17.5) 19.6 (17.0) 19.4 (16.7) 18.8 (16.1) 17.9 (15.2)
7500 20.4 (17.7) 20.2 (17.6) 19.8 (17.0) 19.3 (16.6) 18.9 (16.2) 18.4 (15.7) 17.5 (14.8)
15,000 20.1 (17.4) 19.8 (17.1) 19.5 (16.8) 19.0 (16.3) 18.6 (15.9) 18.1 (15.3) 17.2 (14.4)
30,000 19.9 (17.1) 19.6 (17.0) 19.3 (16.6) 18.8 (16.0) 18.4 (15.6) 17.9 (15.0) 17.0 (14.3)
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