ZHCSJY1A June 2019 – January 2021 ADS125H01
PRODUCTION DATA
A key consideration in the design of an analog input module is the error over the ambient temperature range resulting from the drift of gain, offset, reference voltage, and linearity error. This example assumes the initial offset and gain (including reference voltage error) are user calibrated at TA = 25°C. Table 10-3 shows the maximum drift error of the ADC over the 0°C to +105°C temperature range.
| PARAMETER | ERROR (0°C to +105°C) |
|---|---|
| Offset drift error | 0.00125% |
| Gain drift error | 0.032% |
| Nonlinearity error (over temperature) | 0.001% |
| Reference drift error (REF5025IDGK external reference) | 0.024% |
| Total drift error | 0.05825% |
As shown in Table 10-3, the total drift error is 0.058% when using the REF5025IDGK reference, which satisfies the 0.1% total error design goal.
The ADC gain is programmed to 0.1875. With a 2.5-V reference voltage, the ADC input range is ±2.5 V / 0.1875 = ±13.3 V. However, using ±15-V power supplies, the required headroom of the PGA limits the range to ±12.5 V (which excludes the tolerance of the ±15-V power supplies). The input range satisfies the extended range design target of ±12 V.
The 1-GΩ minimum input impedance of the ADC and the 100-MΩ external pullup resistor meets the input impedance goal of 100 MΩ. The input fault overvoltage requirement (35 V) is met by limiting the input current to the 10-mA maximum specification. The external 5-kΩ series input resistor limits the input current to 7 mA.
The data rate that meets the continuous-conversion, 50-µs acquisition period is 25600 SPS (39 µs actual). If a precise 50-µs conversion period is desired, reduce the clock frequency to the ADC with an external clock source. The clock frequency that produces a precise 50-µs conversion period is 5.76 MHz.
Referring to the data illustrated in Figure 8-3, the effective resolution is 18 bits at data rate = 25600 SPS and gain = 0.1875.