ZHCSIZ6C
October 2018 – June 2019
ADS125H02
PRODUCTION DATA.
1
特性
2
应用
3
说明
功能方框图
4
修订历史记录
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements
7.7
Switching Characteristics
7.8
Typical Characteristics
8
Parameter Measurement Information
8.1
Noise Performance
9
Detailed Description
9.1
Overview
9.2
Functional Block Diagram
9.3
Feature Description
9.3.1
Input Range
9.3.2
Analog Inputs
9.3.2.1
ESD Diodes
9.3.2.2
Input Multiplexer
9.3.2.2.1
Analog Inputs (AIN0, AIN1, AINCOM)
9.3.2.2.2
High-Voltage Power Supply Readback
9.3.2.2.3
Internal VCOM Connection (Default)
9.3.2.2.4
Temperature Sensor
9.3.3
Programmable Gain Amplifier (PGA)
9.3.3.1
PGA Operating Range
9.3.3.2
PGA Monitor
9.3.4
Reference Voltage
9.3.4.1
Internal Reference
9.3.4.2
External Reference
9.3.4.3
AVDD Power-Supply Reference
9.3.4.4
Reference Monitor
9.3.5
Current Sources (IDAC1 and IDAC2)
9.3.6
General-Purpose Inputs and Outputs (GPIOs)
9.3.7
ADC Modulator
9.3.8
Digital Filter
9.3.8.1
Sinc Filter Mode
9.3.8.1.1
Sinc Filter Frequency Response
9.3.8.2
FIR Filter
9.3.8.3
50-Hz and 60-Hz Normal Mode Rejection
9.4
Device Functional Modes
9.4.1
Conversion Control
9.4.1.1
Continuous-Conversion Mode
9.4.1.2
Pulse-Conversion Mode
9.4.1.3
Conversion Latency
9.4.1.4
Start-Conversion Delay
9.4.2
Auto-Zero Mode
9.4.3
Clock Mode
9.4.4
Reset
9.4.4.1
Power-On Reset
9.4.4.2
Reset by Pin
9.4.4.3
Reset by Command
9.4.5
Calibration
9.4.5.1
Offset and Full-Scale Calibration
9.4.5.1.1
Offset Calibration Registers
9.4.5.1.2
Full-Scale Calibration Registers
9.4.5.2
Offset Calibration (OFSCAL)
9.4.5.3
Full-Scale Calibration (GANCAL)
9.4.5.4
Calibration Command Procedure
9.4.5.5
User Calibration Procedure
9.5
Programming
9.5.1
Serial Interface
9.5.1.1
Chip-Select Pins (CS1 and CS2)
9.5.1.2
Serial Clock (SCLK)
9.5.1.3
Data Input (DIN)
9.5.1.4
Data Output/Data Ready (DOUT/DRDY)
9.5.2
Data Ready (DRDY)
9.5.2.1
DRDY in Continuous-Conversion Mode
9.5.2.2
DRDY in Pulse-Conversion Mode
9.5.2.3
Data Ready by Software Polling
9.5.3
Conversion Data
9.5.3.1
Status Byte (STATUS0)
9.5.3.2
Conversion Data Format
9.5.4
Cyclic Redundancy Check (CRC)
9.5.5
Commands
9.5.5.1
General Command Format
9.5.5.2
NOP Command
9.5.5.3
RESET Command
9.5.5.4
START Command
9.5.5.5
STOP Command
9.5.5.6
RDATA Command
9.5.5.7
OFSCAL Command
9.5.5.8
GANCAL Command
9.5.5.9
RREG Command
9.5.5.10
WREG Command
9.5.5.11
LOCK Command
9.5.5.12
UNLOCK Command
9.6
Register Map
9.6.1
Device Identification (ID) Register (address = 00h) [reset = 6xh]
Table 30.
ID Register Field Descriptions
9.6.2
Main Status (STATUS0) Register (address = 01h) [reset = 01h]
Table 31.
STATUS0 Register Field Descriptions
9.6.3
Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
Table 32.
MODE0 Register Field Descriptions
9.6.4
Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
Table 33.
MODE1 Register Field Descriptions
9.6.5
Mode 2 (MODE2) Register (address = 04h) [reset = 00h]
Table 34.
MODE2 Register Field Descriptions
9.6.6
Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
Table 35.
MODE3 Register Field Descriptions
9.6.7
Reference Configuration (REF) Register (address = 06h) [reset = 05h]
Table 36.
REF Register Field Descriptions
9.6.8
Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
Table 37.
OFCAL0, OFCAL1, OFCAL2 Registers Field Description
9.6.9
Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
Table 38.
FSCAL0, FSCAL1, FSCAL2 Registers Field Description
9.6.10
Current Source Multiplexer (I_MUX) Register (address = 0Dh) [reset = FFh]
Table 39.
I_MUX Register Field Descriptions
9.6.11
Current Source Magnitude (I_MAG) Register (address = 0Eh) [reset = 00h]
Table 40.
I_MAG Register Field Descriptions
9.6.12
Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
Table 41.
RESERVED Register Field Descriptions
9.6.13
MODE4 (MODE4) Register (address = 10h) [reset = 50h]
Table 42.
MODE4 Register Field Descriptions
9.6.14
PGA Alarm (STATUS1) Register (address = 11h) [reset = xxh]
Table 43.
STATUS1 Register Field Descriptions
9.6.15
Status 2 (STATUS2) Register (address = 12h) [reset = 0xh]
Table 44.
STATUS2 Register Field Descriptions
10
Application and Implementation
10.1
Application Information
10.1.1
Input Range
10.1.2
Input Overload
10.1.2.1
Input Signal Rate of Change (dV/dt)
10.1.3
Unused Inputs and Outputs
10.2
Typical Applications
10.2.1
±10-V Analog Input Module
10.2.1.1
Design Requirements
10.2.1.2
Detailed Design Procedure
10.2.1.3
Application Curves
10.2.2
Thermocouple Input With High Common-Mode Voltage
10.3
Initialization Setup
11
Power Supply Recommendations
11.1
Power-Supply Decoupling
11.2
Analog Power-Supply Clamp
11.3
Power-Supply Sequencing
11.4
5-V to ±15-V DC-DC Converter
12
Layout
12.1
Layout Guidelines
12.2
Layout Example
13
器件和文档支持
13.1
文档支持
13.1.1
相关文档
13.2
接收文档更新通知
13.3
社区资源
13.4
商标
13.5
静电放电警告
13.6
Glossary
14
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
RHB|32
MPQF130D
散热焊盘机械数据 (封装 | 引脚)
RHB|32
QFND029X
订购信息
zhcsiz6c_oa
zhcsiz6c_pm
9.4
Device Functional Modes
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