ZHCSHW1C March 2018 – January 2019 ADS1260 , ADS1261
PRODUCTION DATA.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LOCK | CRCERR | PGAL_ALM | PGAH_ALM | REFL_ALM | DRDY | CLOCK | RESET |
| R-0h | R/W-0h | R-0h | R-0h | R-0h | R-0h | R-xh | R/W-1h |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | LOCK | R | 0h |
Register Lock Status Indicates register lock status. Register writes are locked by the LOCK command and unlocked by the UNLOCK command. 0: Register write not locked (default) 1: Register write locked |
| 6 | CRCERR | R/W | 0h | CRC Error
Indicates that a CRC error is detected by the ADC. The CRC error bit remains set until cleared by the user. 0: No CRC error 1: CRC error |
| 5 | PGAL_ALM | R | 0h |
PGA Low Alarm Indicates PGA output voltage is below the low limit. The alarm resets at the start of conversion cycles. 0: No Alarm 1: Alarm |
| 4 | PGAH_ALM | R | 0h |
PGA High Alarm Indicates PGA output voltage is above the high limit. The alarm resets at the start of conversion cycles. 0: No Alarm 1: Alarm |
| 3 | REFL_ALM | R | 0h |
Reference Low Alarm Indicates reference voltage is below the low limit. The alarm resets at the start of conversion cycles. 0: No Alarm 1: Alarm |
| 2 | DRDY | R | 0h | Data Ready
Indicates conversion data ready. 0: Conversion data not new since the previous read operation 1: Conversion data new since the previous read operation |
| 1 | CLOCK | R | xh | Clock
Indicates internal or external clock mode. The ADC automatically selects the clock source. 0: ADC clock is internal 1: ADC clock is external |
| 0 | RESET | R/W | 1h | Reset
Indicates ADC reset. Clear the bit to detect next device reset. 0: No reset 1: Reset (default) |