ZHCSHW1C March   2018  – January 2019 ADS1260 , ADS1261

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      框图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Analog Inputs
        1. 9.3.1.1 ESD Diodes
        2. 9.3.1.2 Input Multiplexer
        3. 9.3.1.3 Temperature Sensor
        4. 9.3.1.4 Power-Supply Readback
        5. 9.3.1.5 Inputs Open
        6. 9.3.1.6 Internal VCOM Connection
        7. 9.3.1.7 Alternate Functions
      2. 9.3.2  PGA
        1. 9.3.2.1 PGA Bypass Mode
        2. 9.3.2.2 PGA Voltage Monitor
      3. 9.3.3  Reference Voltage
        1. 9.3.3.1 Internal Reference
        2. 9.3.3.2 External Reference
        3. 9.3.3.3 AVDD - AVSS Reference (Default)
        4. 9.3.3.4 Reference Monitor
      4. 9.3.4  Level-Shift Voltage (VBIAS)
      5. 9.3.5  Burn-Out Current Sources
      6. 9.3.6  Sensor-Excitation Current Sources (IDAC1 and IDAC2)
      7. 9.3.7  General-Purpose Input/Outputs (GPIOs)
      8. 9.3.8  Oversampling
      9. 9.3.9  Modulator
      10. 9.3.10 Digital Filter
        1. 9.3.10.1 Sinc Filter
          1. 9.3.10.1.1 Sinc Filter Frequency Response
        2. 9.3.10.2 FIR Filter
          1. 9.3.10.2.1 FIR Filter Frequency Response
        3. 9.3.10.3 Filter Bandwidth
        4. 9.3.10.4 50-Hz and 60-Hz Normal Mode Rejection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Conversion Control
        1. 9.4.1.1 Continuous-Conversion Mode
        2. 9.4.1.2 Pulse-Conversion Mode
        3. 9.4.1.3 Conversion Latency
        4. 9.4.1.4 Start-Conversion Delay
      2. 9.4.2 Chop Mode
      3. 9.4.3 AC-Excitation Mode
      4. 9.4.4 ADC Clock Mode
      5. 9.4.5 Power-Down Mode
        1. 9.4.5.1 Hardware Power-Down
        2. 9.4.5.2 Software Power-Down
      6. 9.4.6 Reset
        1. 9.4.6.1 Power-on Reset
        2. 9.4.6.2 Reset by Pin
        3. 9.4.6.3 Reset by Command
      7. 9.4.7 Calibration
        1. 9.4.7.1 Offset and Full-Scale Calibration
          1. 9.4.7.1.1 Offset Calibration Registers
          2. 9.4.7.1.2 Full-Scale Calibration Registers
        2. 9.4.7.2 Offset Self-Calibration (SFOCAL)
        3. 9.4.7.3 Offset System-Calibration (SYOCAL)
        4. 9.4.7.4 Full-Scale Calibration (GANCAL)
        5. 9.4.7.5 Calibration Command Procedure
        6. 9.4.7.6 User Calibration Procedure
    5. 9.5 Programming
      1. 9.5.1 Serial Interface
        1. 9.5.1.1 Chip Select (CS)
        2. 9.5.1.2 Serial Clock (SCLK)
        3. 9.5.1.3 Data Input (DIN)
        4. 9.5.1.4 Data Output/Data Ready (DOUT/DRDY)
        5. 9.5.1.5 Serial Interface Auto-Reset
      2. 9.5.2 Data Ready (DRDY)
        1. 9.5.2.1 DRDY in Continuous-Conversion Mode
        2. 9.5.2.2 DRDY in Pulse-Conversion Mode
        3. 9.5.2.3 Data Ready by Software Polling
      3. 9.5.3 Conversion Data
        1. 9.5.3.1 Status byte (STATUS)
        2. 9.5.3.2 Conversion Data Format
      4. 9.5.4 CRC
      5. 9.5.5 Commands
        1. 9.5.5.1  NOP Command
        2. 9.5.5.2  RESET Command
        3. 9.5.5.3  START Command
        4. 9.5.5.4  STOP Command
        5. 9.5.5.5  RDATA Command
        6. 9.5.5.6  SYOCAL Command
        7. 9.5.5.7  GANCAL Command
        8. 9.5.5.8  SFOCAL Command
        9. 9.5.5.9  RREG Command
        10. 9.5.5.10 WREG Command
        11. 9.5.5.11 LOCK Command
        12. 9.5.5.12 UNLOCK Command
    6. 9.6 Register Map
      1. 9.6.1  Device Identification (ID) Register (address = 00h) [reset = xxh]
        1. Table 30. ID Register Field Descriptions
      2. 9.6.2  Device Status (STATUS) Register (address = 01h) [reset = 01h]
        1. Table 31. STATUS Register Field Descriptions
      3. 9.6.3  Mode 0 (MODE0) Register (address = 02h) [reset = 24h]
        1. Table 32. MODE0 Register Field Descriptions
      4. 9.6.4  Mode 1 (MODE1) Register (address = 03h) [reset = 01h]
        1. Table 33. MODE1 Register Field Descriptions
      5. 9.6.5  Mode 2 (MODE2) Register (address = 04h) [reset = 00h]
        1. Table 34. MODE2 Register Field Descriptions
      6. 9.6.6  Mode 3 (MODE3) Register (address = 05h) [reset = 00h]
        1. Table 35. MODE3 Register Field Descriptions
      7. 9.6.7  Reference Configuration (REF) Register (address = 06h) [reset = 05h]
        1. Table 36. REF Register Field Descriptions
      8. 9.6.8  Offset Calibration (OFCALx) Registers (address = 07h, 08h, 09h) [reset = 00h, 00h, 00h]
        1. Table 37. OFCAL0, OFCAL1, OFCAL2 Registers Field Description
      9. 9.6.9  Full-Scale Calibration (FSCALx) Registers (address = 0Ah, 0Bh, 0Ch) [reset = 00h, 00h, 40h]
        1. Table 38. FSCAL0, FSCAL1, FSCAL2 Registers Field Description
      10. 9.6.10 IDAC Multiplexer (IMUX) Register (address = 0Dh) [reset = FFh]
        1. Table 39. IMUX Register Field Descriptions
      11. 9.6.11 IDAC Magnitude (IMAG) Register (address = 0Eh) [reset = 00h]
        1. Table 40. IMAG Register Field Descriptions
      12. 9.6.12 Reserved (RESERVED) Register (address = 0Fh) [reset = 00h]
        1. Table 41. RESERVED Register Field Descriptions
      13. 9.6.13 PGA Configuration (PGA) Register (address = 10h) [reset = 00h]
        1. Table 42. PGA Register Field Descriptions
      14. 9.6.14 Input Multiplexer (INPMUX) Register (address = 11h) [reset = FFh]
        1. Table 43. INPMUX Register Field Descriptions
      15. 9.6.15 Input Bias (INPBIAS) Register (address = 12h) [reset = 00h]
        1. Table 44. INPBIAS Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Input Range
      2. 10.1.2 Input Overload
      3. 10.1.3 Burn-Out Current Source
      4. 10.1.4 Unused Inputs and Outputs
      5. 10.1.5 AC-Excitation
      6. 10.1.6 Serial Interface and Digital Connections
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Initialization Setup
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Analog Power-Supply Clamp
    3. 11.3 Power-Supply Sequencing
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 相关链接
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 术语表
  14. 14机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RHB|32
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 修订历史记录

Changes from B Revision (October 2018) to C Revision

  • Changed Figure 14, Offset Voltage Long-Term Drift to include 2000-hour data Go
  • Changed Figure 31, Voltage Reference Long-Term Drift to include 2000-hour data Go
  • Changed CRC polynomial to correct listing error: changed CRC-8-ATM (HEC): X8 + X2 + X0 + 1 to CRC-8-ATM (HEC): X8 + X2 + X1 + 1Go

Changes from A Revision (May 2018) to B Revision

  • Added 在米6体育平台手机版_好二三四说明书中添加了 ADS1261 器件Go
  • Changed 将 ADS1260 器件从预览更改成了生产数据（有效）Go
  • Added connection options to NC pinsGo
  • Added differential input current specification for gain = 128 in Electrical CharacteristicsGo
  • Added no missing codes specification in Electrical Characteristics Go
  • Changed integral nonlinearity specification for gain 64 and 128 in Electrical CharacteristicsGo
  • Changed integral nonlinearity specification for 40 kSPS mode in Electrical CharacteristicsGo
  • Added offset voltage long-term drift in Electrical CharacteristicsGo
  • Changed voltage reference inputs specification in Electrical Characteristics based on updated characteristicsGo
  • Added voltage reference initial error specification for ADS1260B and ADS1261B in Electrical CharacteristicsGo
  • Added voltage reference temperature drift specification for ADS1260B and ADS1261B in Electrical Characteristics Go
  • Added voltage reference long-term drift in Electrical Characteristics Go
  • Added voltage reference thermal hysteresis in Electrical CharacteristicsGo
  • Added note for PSRR calculation in Electrical CharacteristicsGo
  • Changed th(SCDO2) specification in Switching CharacteristicsGo
  • Changed tp(SCDO2) specification in Switching CharacteristicsGo
  • Added Figure 14, Offset Voltage Long-Term DriftGo
  • Changed Figure 24, Conversion Data Histogram (gain = 4) to 8192 data pointsGo
  • Changed Figure 25, Conversion Data Histogram (gain = 128) to 8192 data points Go
  • Changed Figure 27, Integral Nonlinearity vs Temperature based on updated characteristics Go
  • Changed Figure 28, Integral Nonlinearity Distribution to add gain = 128 Go
  • Changed Figure 29, Integral Nonlinearity vs Reference Voltage to add gain = 64 and 128 Go
  • Added Figure 30, Voltage Reference vs Temperature for ADS1260B, ADS1261B Go
  • Added Figure 31, Voltage Reference Long-Term DriftGo
  • Changed Figure 32, Reference Input Current vs Reference Voltage based on updated characteristicsGo
  • Added Figure 39, CMRR vs Frequency Go
  • Added Figure 40, PSRR vs Frequency Go
  • Added text for Table 2, Effective Resolution (Noise-Free Resolution)Go
  • Changed Table 2, Effective Resolution (Noise-Free Resolution) based on updated characteristicsGo

Changes from * Revision (March 2018) to A Revision

  • Changed 将 ADS1261 器件从预告信息更改成了生产数据（有效）Go
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