ZHCSIS6B September 2018 – December 2018 ADS1278-SP
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 说明 （续）
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Sampling Aperture Matching
- 8.3.2 Frequency Response
- 8.3.3 Phase Response
- 8.3.4 Settling Time
- 8.3.5 Data Format
- 8.3.6 Analog Inputs (AINP, AINN)
- 8.3.7 Voltage Reference Inputs (VREFP, VREFN)
- 8.3.8 Clock Input (CLK)
- 8.3.9 Mode Selection (MODE)
- 8.3.10 Synchronization (SYNC)
- 8.3.11 Power-Down (PWDN)
- 8.3.12 Format[2:0]
- 8.3.13 Serial Interface Protocols
- 8.3.14 SPI Serial Interface
- 8.3.15 Frame-Sync Serial Interface
- 8.3.16 DOUT Modes
- 8.3.17 Daisy-Chaining
- 8.3.18 Modulator Output
- 8.3.19 Pin Test Using Test[1:0] Inputs
- 8.3.20 VCOM Output
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文档支持
- 13机械、封装和可订购信息
7.6 Timing Requirements: SPI Format(6)
For TA = –55°C to 125°C, IOVDD = 1.65 V to 3.6 V, and DVDD = 1.65 V to 1.95 V.| SYMBOL | PARAMETER | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| tCLK | CLK period (1 / fCLK)(1) | 37 | 10,000 | ns | |
| tCPW | CLK positive or negative pulse width | 15 | ns | ||
| tCONV | Conversion period (1 / fDATA)(2) | 256 | 2560 | tCLK | |
| tCD(3) | Falling edge of CLK to falling edge of DRDY | 22 | ns | ||
| tDS(3) | Falling edge of DRDY to rising edge of first SCLK to retrieve data | 1 | tCLK | ||
| tMSBPD | DRDY falling edge to DOUT MSB valid (propagation delay) | 16 | ns | ||
| tSD(3) | Falling edge of SCLK to rising edge of DRDY | 18 | ns | ||
| tSCLK(4) | SCLK period | 1 | tCLK | ||
| tSPW | SCLK positive or negative pulse width | 0.4 | tCLK | ||
| tDOHD(3)(5) | SCLK falling edge to new DOUT invalid (hold time) | 10 | ns | ||
| tDOPD(3) | SCLK falling edge to new DOUT valid (propagation delay) | 32 | ns | ||
| tDIST | New DIN valid to falling edge of SCLK (setup time) | 6 | ns | ||
| tDIHD(5) | Old DIN valid to falling edge of SCLK (hold time) | 6 | ns |
(1) fCLK = 27-MHz maximum.
(2) Depends on MODE[1:0] and CLKDIV selection. See Table 5 (fCLK / fDATA).
(3) Load on DRDY and DOUT = 20 pF.
(4) For best performance, limit fSCLK / fCLK to ratios of 1, 1/2, 1/4, 1/8, etc..
(5) tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is > 4 ns.
(6) Timing parameters are characterized or assured by design for specified temperature but not production tested.
Figure 1. SPI Format Timing Characteristics