8.3.10 Synchronization (SYNC)

The ADS1278-SP can be synchronized by pulsing the SYNC pin low and then returning the pin high. When the pin goes low, the conversion process stops, and the internal counters used by the digital filter are reset. When the SYNC pin returns high, the conversion process restarts. Synchronization allows the conversion to be aligned with an external event, such as the changing of an external multiplexer on the analog inputs, or by a reference timing pulse.

Because the ADS1278-SP converters operate in parallel from the same master clock and use the same SYNC input control, they are always in synchronization with each other. The aperture match among internal channels is typically less than 500 ps. However, the synchronization of multiple devices is somewhat different. At device power-on, variations in internal reset thresholds from device to device may result in uncertainty in conversion timing.

The SYNC pin can be used to synchronize multiple devices to within the same CLK cycle. Figure 69 illustrates the timing requirement of SYNC and CLK in SPI format.

See Figure 70 for the Frame-Sync format timing requirement.

After synchronization, indication of valid data depends on whether SPI or Frame-Sync format was used.

In the SPI format, DRDY goes high as soon as SYNC is taken low; see Figure 69. After SYNC is returned high, DRDY stays high while the digital filter is settling. Once valid data are ready for retrieval, DRDY goes low.

In the Frame-Sync format, DOUT goes low as soon as SYNC is taken low; see Figure 70. After SYNC is returned high, DOUT stays low while the digital filter is settling. Once valid data are ready for retrieval, DOUT begins to output valid data. For proper synchronization, FSYNC, SCLK, and CLK must be established before taking SYNC high, and must then remain running. If the clock inputs (CLK, FSYNC or SCLK) are subsequently interrupted or reset, re-assert the SYNC pin.

For consistent performance, re-assert SYNC after device power-on when data first appear.

Figure 69. Synchronization Timing (SPI Protocol)

Figure 70. Synchronization Timing (Frame-Sync Protocol)