8.3.18 Modulator Output

The ADS1278-SP incorporates a 6th-order, single-bit, chopper-stabilized modulator followed by a multi-stage digital filter that yields the conversion results. The data stream output of the modulator is available directly, bypassing the internal digital filter. The digital filter is disabled, reducing the DVDD current, as shown in Table 13. In this mode, an external digital filter implemented in an ASIC, FPGA, or similar device is required. To invoke the modulator output, tie FORMAT[2:0], as shown in Figure 80. DOUT[8:1] then becomes the modulator data stream outputs for each channel and SCLK becomes the modulator clock output. The DRDY/FSYNC pin becomes an unused output and can be ignored. The normal operation of the Frame-Sync and SPI interfaces is disabled, and the functionality of SCLK changes from an input to an output, as shown in Figure 80.

Figure 80. Modulator Output

In modulator output mode, the frequency of the modulator clock output (SCLK) depends on the mode selection of the ADS1278-SP. Table 13 lists the modulator clock output frequency and DVDD current versus device mode.

Figure 81 shows the timing relationship of the modulator clock and data outputs.

The data output is a modulated 1s density data stream. When V_IN = +V_REF, the 1s density is approximately 80% and when V_IN = –V_REF, the 1s density is approximately 20%.

Figure 81. Modulator Output Timing