ZHCSIS6B September 2018 – December 2018 ADS1278-SP
PRODUCTION DATA.
The test mode feature of the ADS1278-SP allows continuity testing of the digital I/O pins. In this mode, the normal functions of the digital pins are disabled and routed to each other as pairs through internal logic, as shown in Table 14. The pins in the left column drive the output pins in the right column. Note: some of the digital input pins become outputs; these outputs must be accommodated in the design. The analog input, power supply, and ground pins all remain connected as normal. The test mode is engaged by setting the pins TEST [1:0] = 11. For normal converter operation, set TEST[1:0] = 00. Do not use '01' or '10'.
TEST MODE PIN MAP | |
---|---|
INPUT PINS | OUTPUT PINS |
PWDN1 | DOUT1 |
PWDN2 | DOUT2 |
PWDN3 | DOUT3 |
PWDN4 | DOUT4 |
PWDN5 | DOUT5 |
PWDN6 | DOUT6 |
PWDN7 | DOUT7 |
PWDN8 | DOUT8 |
MODE0 | DIN |
MODE1 | SYNC |
FORMAT0 | CLKDIV |
FORMAT1 | FSYNC/DRDY |
FORMAT2 | SCLK |