9.2.2 Detailed Design Procedure

To obtain the specified performance from the ADS1278-SP, the following layout and component guidelines should be considered.

1. Power Supplies: The device requires three power supplies for operation: DVDD, IOVDD, and AVDD. The allowed range for DVDD is 1.65 V to 1.95 V; the range of IOVDD is 1.65 V to 3.6 V; AVDD is restricted to 4.75 V to 5.25 V. For all supplies, use a 10-μF tantalum capacitor, bypassed with a 0.1-μF ceramic capacitor, placed close to the device pins. Alternatively, a single 10-μF ceramic capacitor can be used. The supplies should be relatively free of noise and should not be shared with devices that produce voltage spikes (such as relays, LED display drivers, etc.). If a switching power-supply source is used, the voltage ripple should be low (less than 2 mV) and the switching frequency outside the passband of the converter.
2. Ground Plane: A single ground plane connecting both AGND and DGND pins can be used. If separate digital and analog grounds are used, connect the grounds together at the converter.
3. Digital Inputs: It is recommended to source-terminate the digital inputs to the device with 50-Ω series resistors. The resistors should be placed close to the driving end of digital source (oscillator, logic gates, DSP, etc.) This placement helps to reduce ringing on the digital lines (ringing may lead to degraded ADC performance).
4. Analog/Digital Circuits: Place analog circuitry (input buffer, reference) and associated tracks together, keeping them away from digital circuitry (DSP, microcontroller, logic). Avoid crossing digital tracks across analog tracks to reduce noise coupling and crosstalk.
5. Reference Inputs: It is recommended to use a minimum 10-μF tantalum with a 0.1-μF ceramic capacitor directly across the reference inputs, VREFP and VREFN. The reference input should be driven by a low-impedance source. For best performance, the reference should have less than 3-μV_RMS in-band noise. For references with noise higher than this level, external reference filtering may be necessary.
6. Analog Inputs: The analog input pins must be driven differentially to achieve specified performance. A true differential driver or transformer (ac applications) can be used for this purpose. Route the analog inputs tracks (AINP, AINN) as a pair from the buffer to the converter using short, direct tracks and away from digital tracks. A 1-nF to 10-nF capacitor should be used directly across the analog input pins, AINP and AINN. A low-k dielectric (such as COG or film type) should be used to maintain low THD. Capacitors from each analog input to ground can be used. They should be no larger than 1/10 the size of the difference capacitor (typically 100 pF) to preserve the ac common-mode performance.
7. Component Placement: Place the power supply, analog input, and reference input bypass capacitors as close as possible to the device pins. This layout is particularly important for small-value ceramic capacitors. Larger (bulk) decoupling capacitors can be located farther from the device than the smaller ceramic capacitors.