ZHCSF11B April   2016  – September 2016 ADS127L01

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Serial Interface
    7. 6.7  Switching Characteristics: Serial Interface Mode
    8. 6.8  Timing Requirements: Frame-Sync Master Mode
    9. 6.9  Switching Characteristics: Frame-Sync Master Mode
    10. 6.10 Timing Requirements: Frame-Sync Slave Mode
    11. 6.11 Switching Characteristics: Frame-Sync Slave Mode
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement information
    1. 7.1 Noise Performance
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs (AINP, AINN)
      2. 8.3.2 Digital Filter
        1. 8.3.2.1 Low-Latency Filter
          1. 8.3.2.1.1 Low-Latency Filter Frequency Response
          2. 8.3.2.1.2 Low-Latency Filter Settling Time
        2. 8.3.2.2 Wideband Filter
          1. 8.3.2.2.1 Wideband Filters Frequency Response
          2. 8.3.2.2.2 Wideband Filters Settling Time
      3. 8.3.3 Voltage Reference Inputs (REFP, REFN)
      4. 8.3.4 Clock Input (CLK)
      5. 8.3.5 Out-of-Range-Detect System Monitor
      6. 8.3.6 System Calibration
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operating Modes (HR, LP, VLP)
      2. 8.4.2 Hardware Mode Pins
        1. 8.4.2.1 Interface Selection Pins (FORMAT, FSMODE)
        2. 8.4.2.2 Digital-Filter Path Selection Pins (FILTER[1:0])
        3. 8.4.2.3 Oversampling Ratio Selection Pins (OSR[1:0])
      3. 8.4.3 Start Pin (START)
      4. 8.4.4 Reset and Power-Down Pin (RESET/PWDN)
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI) Programming
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Ready (DRDY/FSYNC)
        4. 8.5.1.4 Data Input (DIN)
        5. 8.5.1.5 Data Output (DOUT)
        6. 8.5.1.6 Daisy-Chain Input (DAISYIN)
        7. 8.5.1.7 SPI Timeout
        8. 8.5.1.8 SPI Commands
          1. 8.5.1.8.1 RESET (0000 011x)
          2. 8.5.1.8.2 START (0000 100x)
          3. 8.5.1.8.3 STOP (0000 101x)
          4. 8.5.1.8.4 RDATA (0001 0010)
          5. 8.5.1.8.5 RREG (0010 rrrr 0000 nnnn)
          6. 8.5.1.8.6 WREG (0100 rrrr 0000 nnnn)
      2. 8.5.2 Frame-Sync Programming
        1. 8.5.2.1 Frame-Sync Master Mode
          1. 8.5.2.1.1 Chip Select (CS) in Frame-Sync Master Mode
          2. 8.5.2.1.2 Serial Clock (SCLK) in Frame-Sync Master Mode
          3. 8.5.2.1.3 Frame-Sync (DRDY/FSYNC) in Frame-Sync Master Mode
          4. 8.5.2.1.4 Data Input (DIN) in Frame-Sync Master Mode
          5. 8.5.2.1.5 Data Output (DOUT) in Frame-Sync Master Mode
          6. 8.5.2.1.6 Daisy-Chain Input (DAISYIN) in Frame-Sync Master Mode
        2. 8.5.2.2 Frame-Sync Slave Mode
          1. 8.5.2.2.1 Chip Select (CS) in Frame-Sync Slave Mode
          2. 8.5.2.2.2 Serial Clock (SCLK) in Frame-Sync Slave Mode
          3. 8.5.2.2.3 Frame-Sync (DRDY/FSYNC) in Frame-Sync Slave Mode
          4. 8.5.2.2.4 Data Input (DIN) in Frame-Sync Slave Mode
          5. 8.5.2.2.5 Data Output (DOUT) in Frame-Sync Slave Mode
          6. 8.5.2.2.6 Daisy-Chain Input (DAISYIN) in Frame-Sync Slave Mode
      3. 8.5.3 Data Format
      4. 8.5.4 Status Word
      5. 8.5.5 Cyclic Redundancy Check (CRC)
        1. 8.5.5.1 Computing the CRC
    6. 8.6 Register Maps
      1. 8.6.1 ID: ID Control Register (address = 00h) [reset = x3h]
      2. 8.6.2 CONFIG: ADC Configuration Register (address = 01h) [reset = 00h]
      3. 8.6.3 OFC0: System Offset Calibration Register 0 (address = 02h) [reset = 00h]
      4. 8.6.4 OFC1: System Offset Calibration Register 1 (address = 03h) [reset = 00h]
      5. 8.6.5 OFC2: System Offset Calibration Register 2 (address = 04h) [reset = 00h]
      6. 8.6.6 FSC0: System Gain Calibration Register 0 (address = 05h) [reset = 00h]
      7. 8.6.7 FSC1: System Gain Calibration Register 1 (address = 06h) [reset = 80h]
      8. 8.6.8 MODE: Mode Settings (address = 07h) [reset = xxh]
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Multiple Device Configuration
        1. 9.1.2.1 Cascaded Configuration
          1. 9.1.2.1.1 SPI interface Mode
          2. 9.1.2.1.2 Frame-Sync interface Mode
        2. 9.1.2.2 Daisy-Chain Configuration
          1. 9.1.2.2.1 Daisy-Chain Operation Using SPI interface Mode
          2. 9.1.2.2.2 Daisy-Chain Operation Using Frame-Sync interface Mode
        3. 9.1.2.3 Synchronizing Devices
      3. 9.1.3 ADC Input Driver
        1. 9.1.3.1 Antialiasing Filter
        2. 9.1.3.2 Input Driver Selection
        3. 9.1.3.3 Amplifier Stability
      4. 9.1.4 Modulator Saturation
      5. 9.1.5 ADC Reference Driver
        1. 9.1.5.1 Single Chip Solution: REF6xxx
        2. 9.1.5.2 Multichip Solution: REF50xx + OPA320
      6. 9.1.6 Driving LVDD With an External Supply
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Do's and Don'ts
    4. 9.4 Initialization Setup
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Sequencing
    2. 10.2 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7 Parameter Measurement information

7.1 Noise Performance

Adjust the oversampling ratio (OSR) to control the data rate and change the digital filter in order to optimize the noise performance of the ADS127L01. Hardware control pins offer four oversampling options and three selectable digital filter options to configure the ADC for a specific bandwidth of interest. When averaging is increased by reducing the data rate (increasing the OSR), the in-band noise drops as more samples from the modulator are averaged to yield one conversion result. Table 1 and Table 2 summarize the device noise performance across the various oversampling and digital filter options. Wideband 1 filter has a filter transition band of (0.45 to 0.55) fDATA, and Wideband 2 filter has a filter transition band of (0.40 to 0.50) fDATA. Data are representative of typical noise performance at TA = 25°C with an external 2.5-V reference. Data shown are the result of one standard deviation of the readings with the inputs shorted together and biased to midsupply. A minimum of 1,000 consecutive readings are used to calculate the VRMS_noise voltage noise for each measurement. Equation 1 is used to convert the noise in VRMS_noise to SNR, and Equation 2 is used to convert the noise in VRMS_noise to ENOB. The peak-to-peak noise for the Low-latency filter is defined as VPP_noise.

Equation 1. SNR = 20 × log (VREF × 0.7071 / VRMS_noise)
Equation 2. ENOB = In (2 x VREF / VRMS_noise) / In (2)

Table 1. Wideband Filters Performance Summary
at AVDD = 3.0 V, DVDD = 1.8 V, and 2.5-V Reference

MODE DATA RATE (SPS) OSR TRANSITION BAND PASS BAND (kHz) SNR
(dB)		 VRMS_noise (μVRMS) ENOB IDVDD
(mA)
High-resolution
(HR)		 512,000 32 Wideband 1 filter 230.4 103.7 11.61 18.72 7.50
Wideband 2 filter 204.8 104.1 10.64 18.84
256,000 64 Wideband 1 filter 115.2 107.3 7.61 19.33 4.35
Wideband 2 filter 102.4 107.7 7.25 19.40
128,000 128 Wideband 1 filter 57.6 110.4 5.35 19.83 2.80
Wideband 2 filter 51.2 110.9 5.06 19.91
64,000 256 Wideband 1 filter 28.8 113.4 3.79 20.33 2.00
Wideband 2 filter 25.6 113.9 3.58 20.41
Low-power
(LP)		 256,000 32 Wideband 1 filter 115.2 103.9 11.27 18.76 3.80
Wideband 2 filter 102.4 104.7 10.31 18.89
128,000 64 Wideband 1 filter 57.6 107.6 7.38 19.37 2.25
Wideband 2 filter 51.2 108.1 6.96 19.45
64,000 128 Wideband 1 filter 28.8 110.7 5.18 19.88 1.50
Wideband 2 filter 25.6 111.1 4.95 19.95
32,000 256 Wideband 1 filter 14.4 113.7 3.67 20.38 1.10
Wideband 2 filter 12.8 114.1 3.47 20.46
Very-low-power
(VLP)		 128,000 32 Wideband 1 filter 57.6 104.1 11.01 18.79 1.95
Wideband 2 filter 51.2 104.9 10.11 18.92
64,000 64 Wideband 1 filter 28.8 107.8 7.20 19.41 1.20
Wideband 2 filter 25.6 108.3 6.80 19.49
32,000 128 Wideband 1 filter 14.4 110.9 5.07 19.91 0.80
Wideband 2 filter 12.8 111.3 4.81 19.99
16,000 256 Wideband 1 filter 7.2 113.9 3.59 20.41 0.60
Wideband 2 filter 6.9 114.3 3.41 20.48

Table 2. Low-Latency Filter Performance Summary
at AVDD = 3.0 V, DVDD = 1.8 V, and 2.5-V Reference

MODE DATA RATE
(SPS)		 OSR -3-dB BANDWIDTH (kHz) SNR
(dB)		 VRMS_noise (μVRMS) ENOB VPP_noise (μVPP) IDVDD
(mA)
High-resolution
(HR)		 512,000 32 101.8 107.6 7.40 19.37 64.67 1.60
128,000 128 50.6 110.8 5.12 19.90 44.11 1.39
32,000 512 13.7 116.2 2.74 20.80 24.14 1.33
8,000 2048 3.5 122.0 1.41 21.76 11.32 1.32
Low-power
(LP)		 256,000 32 50.9 107.8 7.22 19.40 61.99 0.85
64,000 128 25.3 111.0 4.97 19.94 46.79 0.75
16,000 512 6.9 116.5 2.65 20.85 22.05 0.73
4,000 2048 1.7 122.2 1.37 21.80 10.73 0.72
Very-low-power
(VLP)		 128,000 32 25.5 108.1 6.97 19.45 65.57 0.50
32,000 128 12.7 111.3 4.80 19.99 39.64 0.44
8,000 512 3.4 116.7 2.57 20.89 20.27 0.41
2,000 2048 0.9 122.4 1.34 21.83 10.73 0.40
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