8.3.1 Analog Inputs (AINP, AINN)

The ADS127L01 measures the differential input signal V_IN = (V_AINP – V_AINN) against the differential reference V_REF = (V_REFP – V_REFN). The most positive measurable differential input is +V_REF and the most negative measurable differential input is –V_REF.

For optimum performance, drive the ADS127L01 inputs differentially, centered around a common-mode voltage of AVDD / 2. Alternatively, if the signal is of pseudo-differential nature, the negative input can be held at a constant voltage other than 0 V (typically AVDD / 2), and the voltage on the positive input can change. Figure 58 and Figure 59 show examples of both fully-differential and pseudo-differential signals, respectively.

Figure 58. Fully-Differential Input Signal

Figure 59. Pseudo-Differential Input Signal

Electrostatic discharge (ESD) diodes to AVDD and AGND protect the inputs. To prevent the ESD diodes from turning on, the absolute voltage on any input must stay within the range provided by Equation 3:

The analog input pins, AINP and AINN, at the front end of the converter are connected directly to the switched-capacitor sampling network to measure the input voltage. Figure 60 shows a conceptual diagram of the modulator circuit charging and discharging the sampling capacitor through switches, although the actual implementation is slightly different. The sampling time (t_CLK / 2) is equivalent to half the master clock period, and is the inverse of the modulator sampling frequency.

Figure 60. Equivalent Analog Input Circuitry

The average load presented by the switched-capacitor input can be modeled with an effective differential impedance, as shown in Figure 61. The effective impedance is a function of the modulator clock, and is equal to the master clock, f_CLK. The ADS127L01 samples the input at very high speeds, and does not include an integrated buffer; a suitable driver must be used. See the Application and Implementation section for recommended driver circuit designs.

Figure 61. Effective Input Impedance

The ADC sampling network is connected to a delta-sigma modulator used to convert the analog input voltage into a data bit stream. The modulator is third-order, with a multibit quantizer that runs at the modulator clock frequency, f_MOD, equal to the master clock frequency, f_CLK.

8.3.2 Digital Filter

The ADS127L01 offers three selectable digital filters to perform both filtering and decimation of the digital data stream coming from the modulator. The oversampling ratio (OSR) and digital-filter selection sets the overall frequency response for the data converter. The available filter options for the ADS127L01 are:

• Low-latency sinc filter (LL)
• Wideband finite impulse response (FIR) filter with a transition band of (0.45 to 0.55) × f_DATA (WB1)
• Wideband finite impulse response (FIR) filter with a transition band of (0.40 to 0.50) × f_DATA (WB2)

Use the hardware FILTER[1:0] pins shown in Table 11. Each filter has four OSR options (the ratio of the modulator sampling to the output data rate, or f_MOD / f_DATA), shown in Table 12, that are selectable through hardware OSR[1:0] pins. The low-latency sinc filter is a cascaded sinc5 and sinc1 filter, and provides OSR options to achieve data rates ranging from 8 kSPS to 512 kSPS when operating from a 16.384-MHz master clock. The two Wideband filters use a multistage FIR topology to provide linear phase response with very low pass-band ripple and high stop-band attenuation. Wideband filters 1 and 2 provide four OSRs to achieve data rates ranging from 64 kSPS to 512 kSPS when operating from a 16.384-MHz master clock.

Select the filter and data rate when START is low, or take the START or RESET/PWDN pin low and back high after a filter-path or data-rate change. If software commands are used to control conversions, use the STOP and START commands after a change to the filter path selection or the data rate. If a conversion is in process during a filter-path or data-rate change, the output data are not valid and must be discarded.

8.3.2.1 Low-Latency Filter

The low-latency sinc filter consists of two stages: a fixed-decimation, sinc5 filter, followed by a variable-decimation, sinc1 filter. The first-stage, sinc5 digital filter decimates by a fixed value of 32. When using OSR 32, the first-stage digital filter bypasses the second filter stage, and has a sinc5 frequency response profile. The second digital-filter stage provides an additional decimation of 4, 16, or 64 to create overall decimation options of 128, 512, and 2048. Together, the two stages create four selectable, Low-latency, filter data rates when operated from a 16.384-MHz clock: 512 kSPS, 128 kSPS, 32 kSPS, and 4 kSPS.

8.3.2.1.1 Low-Latency Filter Frequency Response

The low-pass filtering effect of the sinc filter sets the overall frequency response of the ADC when in low-latency filter mode. The frequency response of OSR 32 is from only the sinc5 filter stage. The frequency response of OSR 128, 512, or 2048 is the product of the sinc5 first-stage and sinc1 second-stage frequency responses. The overall filter response is given in Equation 4:

Equation 4.

where

• f = signal frequency
• f_CLK = ADC master clock frequency = ADC modulator clock frequency
• N = Second-stage oversampling = 1 (OSR 32), 4 (OSR 128), 16 (OSR 512), or 64 (OSR 2048)

The inherent nature of the sinc filter response begins to attenuate frequencies as the signal moves away from dc. The pass band droop for inband ac signals makes the low-latency filter less ideal for ac signals.

As shown in Figure 62 and Figure 63, when OSR is set to 32, the digital filter frequency response follows a sinc5 transfer function with nulls occurring at f_DATA and at multiples thereof. At the null frequencies, the filter has zero gain. Convert the x-axis from the data rate, f_DATA, to terms of the master clock, f_CLK, by using Equation 5:

Equation 5. f_DATA = f_CLK / OSR

Figure 62. Low-Latency Filter Frequency Response
(OSR 32)

Figure 63. Low-Latency Filter Frequency Response
(OSR 32) to f_CLK

Adjust the digital-filter response by changing the OSR or the master clock, f_CLK. Noise tradeoffs are made with signal bandwidth and filter latency.

Selecting an OSR other than 32 superimposes new nulls from the second-stage sinc1 filter over the nulls produced by the sinc5 stage. The end result is a combined frequency response from a sinc5 function at OSR 32 with nulls created from the sinc1 second stage at f_DATA and multiple thereof.

Figure 64 and Figure 65 illustrate the normalized frequency response of the Low-latency filter across all four OSR settings. OSR 32 follows a sinc5 frequency response, as highlighted in Figure 62. OSR 128, OSR 512, and OSR 2048 show a combined sinc5 and sinc1 response.

Figure 66, Figure 67, and Figure 68 illustrate the frequency response of OSR 128, OSR 512, and OSR 2048, respectively.

The Low-latency filter uses a multiple-stage, linear-phase, digital filter. Linear-phase filters exhibit constant delay time versus input frequency (also known as constant group delay). This feature of linear phase filters means that the time delay from any instant of the input signal to the corresponding same instant of the output data is constant and independent of the input-signal frequency. This behavior results in essentially zero phase error when measuring multitone signals.

Figure 64. Low-Latency Filter Frequency Response

Figure 66. Low-Latency Filter Frequency Response
(OSR 128) to f_CLK

Figure 68. Low-Latency Filter Frequency Response
(OSR 2048) to f_CLK

Figure 65. Low-Latency Filter Frequency Response
to 0.5 × f_IN / f_DATA

Figure 67. Low-Latency Filter Frequency Response
(OSR 512) to f_CLK

8.3.2.1.2 Low-Latency Filter Settling Time

The Low-latency filter takes several conversion cycles to provide fully-settled data following a START pin low-to-high transition or a START command. The OSR setting determines the exact number of conversion cycles for first new available data, as shown in Table 3. In SPI mode, the DRDY signal remains high until settled data are available. After settled data are available, a high-to-low transition on DRDY takes place. In frame-sync mode, DOUT shifts zeroes until settled data are available. Figure 69 shows the relationship between START to the first settled available data for SPI and frame-sync interface mode. See the Start Pin (START) section for exact timing for the START pin to first available data.

Figure 69. START to First Available Data

When applying an asynchronous step input to a converting ADS127L01, the output shift register does not gate data during digital-filter settling. The step-input-setting timing diagram shown in Figure 70 illustrates the converter step response with an asynchronous step input. The time that the analog input must be stable varies depending on the OSR. Table 3 summarizes the settling time of the Low-latency filter when a step input is applied to the input.

Figure 70. Asynchronous Step-Input Settling Time

Table 3. Low-Latency Filter Settling Time (Conversion Latency)

OSR	SETTLING TIME FROM START (tCLK Periods)	INPUT SETTLING (DRDY or FSYNC Pulses)
32	160	5
128	288	3
512	672	2
2048	2208	2

8.3.2.2 Wideband Filter

The two Wideband filters use a multistage FIR topology to provide linear phase response with minimal pass-band ripple and high stop-band attenuation. The filters are well suited for measuring high-frequency ac signals while still maintaining excellent dc accuracy. Both Wideband filter options offer the same four OSR options; 32, 64, 128, and 256. The difference is in the transition band. When these four OSRs are paired with a 16.384-MHz clock, four selectable Wideband filter data rates are created: 512 kSPS, 256 kSPS, 128 kSPS, and 64 kSPS.

8.3.2.2.1 Wideband Filters Frequency Response

Figure 71 shows the frequency response of the Wideband 1 filter with a transition band of (0.45 to 0.55) × f_DATA normalized to the output data rate, f_DATA. Figure 72 shows the frequency response of the Wideband 2 filter with a transition band of (0.40 to 0.50) × f_DATA normalized to the output data rate, f_DATA. These plots are valid for all of the data rates available on the ADS127L01. Substitute the selected data rate, f_DATA (calculated using Equation 5), to express the x-axis in absolute frequency. Figure 73 overlaps the transition band of the Wideband 1 and Wideband 2 filters, showing the difference in frequency response. The Wideband 2 filter frequency response is designed to attenuate out-of-band signals more than –116 dB by the Nyquist frequency (0.5 × f_DATA) to reduce the effects of aliasing near the transition band.

	FILTER[1:0] = 00

Figure 71. Wideband 1 Filter Frequency Response

Figure 73. Wideband Filters Transition Band

	FILTER[1:0] = 01

Figure 72. Wideband 2 Filter Frequency Response

The pass-band ripple for the two digital filters are shown in Figure 74 and Figure 75.

	FILTER[1:0] = 00

Figure 74. Pass Band Ripple for Wideband 1 Filter

	FILTER[1:0] = 01

Figure 75. Pass Band Ripple for Wideband 2 Filter

The overall frequency response repeats at the modulator sampling rate, which is the same as the input clock frequency, f_CLK. Figure 76 shows the response with the fastest data rate selected (512 kSPS when f_CLK = 16.384 MHz).

Figure 76. Extended Frequency Response of Wideband 1 Filter (OSR 32)

The Wideband filters use a multiple-stage, linear-phase, digital-filter architecture. Linear-phase filters exhibit constant delay time versus input frequency (also known as constant group delay). This feature of linear phase filters means that the time delay from any instant of the input signal to the corresponding same instant of the output data is constant and independent of the input-signal frequency. This behavior results in essentially zero phase error when measuring multitone signals.

8.3.2.2.2 Wideband Filters Settling Time

The Wideband filters fully settle before outputting data after the START pin low-to-high transition or a START command is issued. The settling time of the Wideband filters is 84 conversion cycles; the DRDY signal idles high and does not assert until new settled data are available in SPI interface mode. In frame-sync interface mode, the output shift register outputs zeroes in place of the conversion data for 84 conversion cycles until the first settled data are available. A step input on the analog input requires multiple conversions to settle if START is not pulsed, or if the START command is not issued. Figure 77 shows the settling response with the x-axis normalized to conversions or DRDY/FSYNC cycles.

Figure 77. Step Response For Wideband Filters

Figure 78 and Figure 79 plot the undershoot and overshoot from the Wideband digital filter during an input step function.

Figure 78. Wideband Filters Step-Response Undershoot

Figure 79. Wideband Filters Step-Response Overshoot

8.3.3 Voltage Reference Inputs (REFP, REFN)

The ADC requires the connection of an external reference voltage for operation. The voltage reference for the device is the differential voltage between REFP and REFN: V_REF = (V_REFP – V_REFN). The reference inputs are not buffered and use a sampling structure similar to that of the analog inputs, with the equivalent circuitry on the reference inputs shown in Figure 80. The load across REFP and REFN is presented by the switched-capacitor in parallel with a 6.4-kΩ resistor, and is modeled with an effective impedance (Z_eff) proportional to the master clock, f_CLK, as shown in Figure 81.

Figure 80. Equivalent Reference Input Circuitry

Figure 81. Effective Reference Impedance

ESD diodes protect the reference inputs. To keep these diodes from turning on, make sure the voltages on the reference pins do not go below AGND by more than 0.3 V, and do not exceed AVDD by 0.3 V. Use external Schottky clamp diodes or series resistors to limit the input current to safe values if the reference input may exceed the absolute maximum ratings (see the Absolute Maximum Ratings table).

A high-quality reference voltage with the appropriate drive strength is required for achieving the best performance from the ADS127L01. Noise and drift on the reference degrade overall system performance. Use a minimum parallel combination of 10-µF and 0.1-µF ceramic bypass capacitors directly across the reference inputs, REFP and REFN. Place these capacitors as close as possible to the device on the layout. See the Application Information section for example reference circuits.

8.3.4 Clock Input (CLK)

The ADS127L01 requires an external clock for operation. This clock signal is used for the sampling network of the modulator without any prescalers or dividers, and for the timing for the digital filter. Drive the ADC with an external clock by applying the clock input to the CLK pin. At the maximum data rate, the clock input is 16.384 MHz for HR mode, 8.192 MHz for LP mode, and 4.096 MHz for VLP mode.

A high-quality, low-jitter clock is essential for optimum performance measuring the high-frequency input signals. Any uncertainty during sampling of the input from clock jitter limits the maximum achievable SNR. For example, uses an external clock with better than 10 ps_rms jitter for a 200-kHz f_IN. For a lower f_IN, the target jitter requirement can be relaxed by –20 dB per decade. At f_IN = 20 kHz, use a clock with better than 100-ps_rms jitter.

The selection of the external clock frequency (f_CLK) does not affect the resolution of the ADS127L01. The output data rates scale with f_CLK frequency down to a minimum clock frequency of f_CLK = 100 kHz. Use a slower f_CLK to reduce the ADC power consumption and relax the requirements of an external ADC drive circuit on the analog input and reference input.

Crystal clock oscillators are the recommended clock source. Make sure to avoid excess ringing on the clock input. A series resistor placed at the external clock buffer output often helps to reduce overshoot.

8.3.5 Out-of-Range-Detect System Monitor

An out-of-range-detect system-monitor bit (INP) is available in the status word (see the Status Word section). The out-of-range detect bit flags (INP = 1) when the input exceeds the positive or negative full-scale range, set by V_REF, with each conversion result. The input is monitored using an analog comparator. The flag is issued when the full-scale range is exceeded without waiting for the conversions to propagate through the digital filter. The INP bit is used for narrow out-of-range input glitches that may or may not be removed by the ADC digital filter.

8.3.6 System Calibration

The ADC incorporates optional offset- and gain-calibration registers to system-calibrate the ADC and signal chain when in SPI interface mode. Enable the offset calibration register by setting FSC bit (bit 5 in the Configuration register) to 1, and enable the gain calibration register by setting OFC bit (bit 4 in the Configuration register) to 1. The programmable offset calibration value is 24 bits wide, and the gain calibration value is 16 bits wide. Use calibration to correct internal ADC errors or overall system errors. Calibration is only supported through direct user calibration, requiring the user to calculate and write the correction values to the calibration registers. Perform a system offset calibration before full-scale calibration. After power-up, but before calibrating, wait for the power supplies and reference voltage to fully settle.

As shown in Figure 82, the value of the offset calibration register is subtracted from the filter output, and then multiplied by the full-scale register value. The data are then clipped to a 24-bit value to provide the final output.

Figure 82. ADC Calibration Block Diagram

Equation 6 shows the internal calibration on the data result.

The ADC offset calibration word is 24 bits, consisting of three 8-bit registers (OFC2, OFC, 1 OFC0), as shown in Table 4. The offset value is twos complement format with a maximum positive value equal to 7FFFFFh (for negative offset), and a maximum negative value equal to 800000h (for positive offset). A register value equal to 000000h has no offset correction. For offset calibration, short the ADC inputs or system inputs, and average the conversions; averaging reduces noise for a more accurate calibration. Write the average value to the offset calibration registers. The ADC subtracts the value from the conversion result.

The ADC gain calibration word is 16 bits consisting of two 8-bit registers (FSC1, FSC0), as shown in Table 5. The full-scale calibration value is twos compliment, with a unity-gain correction factor at a register value equal to 8000h. Table 6 shows register values for selected gain factors.

For gain calibration, apply a dc calibration voltage that is less than positive full-scale voltage in order to avoid clipped codes (V_IN < +FSR), and average the conversions to reduce noise for a more accurate calibration. Gain calibration is computed as shown in Equation 7, after offset error is removed.

If the actual code is higher than the expected value, then the calculated calibration value is less than 8000h, and the ADC gain is subsequently reduced. Write the calibration value to the gain calibration registers.

8.4.1 Operating Modes (HR, LP, VLP)

The ADS127L01 offers three operational modes: high-resolution (HR), low-power (LP), and very-low-power (VLP). These modes optimize power consumption by restricting the maximum master-clock frequency (f_CLK) controlling the data rate. The status of the HR pin determines if the device is in HR mode or LP mode. Enter VLP mode by setting the ADS127L01 in LP mode, and increasing the value of the external R_EXT power scaling resistor from 60.4 kΩ to 120 kΩ. The tolerance on the R_EXT power-scaling resistor must be 1% or better. The analog current consumed by AVDD and LVDD decreases when in LP mode, and decreases further in VLP mode, with a tighter restriction on maximum master-clock frequency. Table 7 details the HR pin and REXT settings for each operating mode in the ADS127L01.

8.4.2 Hardware Mode Pins

The ADS127L01 uses two-state hardware mode pins for ADC configuration. The operating mode, interface selection, digital filter selection, and oversampling ratio (OSR) are all controlled through hardware pins. These pins are constantly monitored, and set by either pulling them high to DVDD, or low to DGND. Use pull-up or pull-down 100-kΩ resistors, or directly tie the pins to microcontroller or DSP I/O lines to set the state of the pins. When a change is sensed on the hardware mode pins after power-up, the ADC automatically issues a reset. To ensure synchronization, issue a software reset command, or pulse the RESET/PWDN pin following the mode change delay, t_d(MD).

When using the SPI interface mode, DRDY is held high after a mode change occurs until settled data are ready; see Figure 83 and Table 8.

Figure 83. Mode Change Timing (SPI Interface)

In Frame-sync intreface mode, the DOUT pins are held low after a mode change occurs until settled data are ready; see Figure 84 and Table 9. Data can be read from the device to detect when DOUT changes, indicating that data are valid.

Figure 84. Mode Change Timing (Frame-Sync Interface)

8.4.3 Start Pin (START)

The START pin controls the start and stop of ADC conversions used for converter synchronization. Take the START pin low to stop conversions and reset the digital filter. Pull START high to start or restart the conversions.

Synchronization allows the conversion to be aligned with an external event, such as the changing of an external multiplexer on the analog inputs. The START pin is also used to synchronize multiple devices to within the same CLK cycle.

Figure 85 and Figure 86 illustrate the timing requirement for the START pin with respect to CLK in SPI and frame-sync interface modes. After synchronization, indication of valid data depends on whether SPI or frame-sync interface mode is used.

In the SPI interface mode, DRDY goes high as soon as START is taken low, as shown in Figure 85. After START is returned high, DRDY stays high while the digital filter completes reset and settles. After valid data are ready for retrieval, DRDY goes low.

Figure 85. Synchronization Timing (SPI Interface)

In frame-sync interface, DOUT goes low as soon as START is taken low, as shown in Figure 86. After START is returned high, the following FSYNC rising edge releases the digital filter from reset to begin conversions. DOUT stays low while the digital filter is settling. Data are ready for retrieval on DOUT after the digital filter settles. For proper synchronization, FSYNC, SCLK, and CLK must be established before taking START high, and must then remain running. If either CLK, FSYNC or SCLK are interrupted or reset, reassert the START pin.

Figure 86. Synchronization Timing (Frame-Sync Interface)

In addition to the START pin, START and STOP commands are also available to control the start and stop of conversions, but only when using the SPI interface. Using the commands requires that the hardware START pin is tied low the entire time. The START command is also used to synchronize multiple ADS127L01s sharing the same SPI interface. See the SPI Commands section for information on using the START and STOP commands to control ADC conversions.

8.4.4 Reset and Power-Down Pin (RESET/PWDN)

The RESET/PWDN pin has two functions, depending on the amount of time the pin is held in a low state. If RESET/PWDN is low for < 2¹⁵ – 1 CLK periods, the ADS127L01 resets both the digital filter and register contents to default settings. The low-to-high transition of the RESET/PWDN pin brings the ADS127L01 out of reset by completing the digital filter reset, as shown in Figure 87 and Figure 88.

Figure 87. Reset Timing (SPI Interface)

Figure 88. Reset Timing (Frame-Sync Interface)

If RESET/PWDN is low for > 2¹⁵ – 1 CLK periods, the ADS127L01 enters power-down mode where both the analog and digital circuitry is completely deactivated. The digital inputs are internally disabled so there is no concern in driving the pins.

Use individual 1-MΩ pull-down resistors placed on CAP3 to DGND, SCLK to DGND, and DRDY/FSYNC to DGND if power-down mode is planned to be used. These resistors help discharge voltage when the device is placed in power-down mode. Shut down the CLK and SCLK in power-down mode to avoid additional power consumption.

Return the RESET/PWDN pin high to exit power-down mode. As shown in Figure 89 and Figure 90, a minimum of 2¹⁵ + 37 master clock periods must elapse before the device exits power-down mode and begins sampling when using SPI interface mode. DRDY stays high after exiting power-down mode while the digital filter settles.

Figure 89. Power-Down Timing (SPI Interface)

A minimum of 2¹⁵ + 7 master clock periods must elapse before the device exits power-down mode to begin sampling, when in Frame-Sync interface mode, as shown in Figure 90 and Table 18. When using Frame-Sync interface mode, DOUT will read back low while the digital filter settles.

Figure 90. Power-Down Timing (Frame-Sync Interface)

8.5.1 Serial Peripheral Interface (SPI) Programming

The SPI-compatible serial interface of the device is used to read conversion data, read and write the device configuration registers, and control device operation. Only SPI mode 1 (CPOL = 0, CPHA = 1) is supported. The interface consists of five control lines (CS, SCLK, DIN, DOUT, and DRDY/FSYNC), but the interface is operational with only four control lines. If the serial bus is not shared with any other device, CS can be tied low permanently so that only signals SCLK, DIN, DOUT and DRDY/FSYNC are required to communicate with the device.

8.5.1.3 Data Ready (DRDY/FSYNC)

In SPI interface mode, DRDY/FSYNC is an active-low, new-data-ready indicator for when a new conversion result is ready for retrieval. When DRDY/FSYNC transitions low, new conversion data are ready. The DRDY/FSYNC signal transitions from low to high with the first SCLK falling edge, as shown in Figure 91. When no data are read during continuous conversion mode, DRDY/FSYNC remains low but pulses high for a duration of 2 · t_CLK before the next DRDY/FSYNC falling edge. The DRDY/FSYNC pin is always actively driven, even when CS is high.

A new conversion result is loaded into the output shift register before DRDY transitions from high to low. The LSB of the previous data word must be read at least 4 · t_CLK before the next DRDY falling edge. This delay is known as keep-out time (t_KO). Keep SCLK low during t_KO until the next conversion result is ready for retrieval, as shown in Figure 91.

Figure 91. SPI Keep-Out Time (t_KO)

8.5.1.8 SPI Commands

The ADS127L01 provides flexible configuration, including commands and configurable registers, only when using the SPI interface. The commands, summarized in Table 19, are stand-alone and configure the operation of the ADS127L01. Each command is a single byte, except for the register read and write operations that require two or more bytes. CS must remain low for the entire command operation (especially for multibyte commands). Take CS high during a opcode command to abort the command.

Table 19. Command Definitions

COMMAND	DESCRIPTION	FIRST BYTE	SECOND BYTE
System Commands
RESET	Reset the device	0000 011x
START	Start or restart (synchronize) conversions	0000 100x
STOP	Stop conversion	0000 101x
Data Read Commands
RDATA	Read data by command	0001 0010
Register Commands
RREG	Read (nnnn + 1) registers starting at address rrrr	0010 rrrr	0000 nnnn
WREG	Write (nnnn + 1) registers starting at address rrrr	0100 rrrr	0000 nnnn

8.5.1.8.1 RESET (0000 011x)

The RESET command halts conversions and resets the ADC to power-on-reset values. During this time, the digital filter resets, requiring an additional power-up time for conversions to begin. The RESET command is decoded by the ADS127L01 on the seventh falling edge of SCLK. For more information, refer to the Reset and Power-Down Pin (RESET/PWDN) section.

8.5.1.8.2 START (0000 100x)

The START command starts conversions and resynchronize the device. When conversions are stopped, either at power-up or following a STOP command, issue a START command to begin ADC conversions. Issuing a START command restarts the conversions by resetting the digital filters. During the reset period, DRDY/FSYNC does not toggle. The START command is decoded by the ADS127L01 on the seventh falling edge of SCLK. The START pin must be held low if the START and STOP commands are used. For more information, refer to the Start Pin (START) section.

8.5.1.8.3 STOP (0000 101x)

The STOP command places the ADC in an idle state where the modulator stops converting. The STOP command is decoded by the ADS127L01 on the seventh falling edge of SCLK. The START pin must be held low if the START and STOP commands are used.

8.5.1.8.4 RDATA (0001 0010)

The RDATA command reloads the output shift register to the MSB of the most recent data. The RDATA command is decoded on the eighth SCLK falling edge, and begins shifting out the MSB of the data word on DOUT on the ninth SCLK.

8.5.1.8.5 RREG (0010 rrrr 0000 nnnn)

The RREG command reads the number of bytes specified by nnnn (number of registers to be read – 1) from the device configuration register, starting at register address rrrr. The command is completed after nnnn + 1 bytes are clocked out after the RREG command byte. For example, the command to read three registers (nnnn = 0010) starting at register address 00h (rrrr = 0000) is 0010 0000 0000 0010 as shown in Figure 92. The communication length must be extended by the proper number of SCLKs to shift register contents out.

Figure 92. Read from Register

8.5.1.8.6 WREG (0100 rrrr 0000 nnnn)

The wREG command writes the number of bytes specified by nnnn (number of registers to be written – 1) to the device configuration register, starting at register address rrrr. The command is completed after nnnn + 1 bytes are clocked in after the WREG command byte. For example, the command to write two registers (nnnn = 0001) starting at register address 01h (rrrr = 0001) is 0100 0001 0000 0001 as shown in Figure 93. Two bytes follow the command to write the contents to the registers. The frame must extend by the proper number of SCLKs to write data to the registers.

Figure 93. Write to Register

8.5.2 Frame-Sync Programming

Frame-sync interface is similar to the interface often used on audio ADCs. The ADS127L01 offers both frame-sync master and frame-sync slave modes that are selectable using the FSMODE pin. In frame-sync format, commands and register assignments are not available. Tie DIN low to DGND.

8.5.3 Data Format

The ADS127L01 provides either a 24-bit or 32-bit output word, 24 bits of which are data in binary twos complement format with an optional eight LSBs containing status word information. The size of one code (LSB) is calculated using Equation 8:

A positive full-scale input [V_IN ≥ (+FS – 1 LSB) = (V_REF – 1 LSB)] produces an output code of 7FFFFFh, and a negative full-scale input (V_IN ≤ –FS = –V_REF ) produces an output code of 800000h. The output clips at these codes for signals that exceed full-scale.

Table 20 summarizes the ideal output codes for different input signals.

8.5.4 Status Word

Trailing the 24 bits of data is an optional 8-bit status word. The status word provides a real-time update of internal system monitors and data integrity. By default, the contents are a mixture of 4-bit CRC data integrity and system monitors. Alternatively, the status word can be set to output an 8-bit CRC without the system monitors. The CRCB bit in the CONFIG regsiter controls the status word contents. Set the CRCB bit to 0 for the status word to contain 4-bit CRC [bits 7:4], one bit [bit 3] to monitor out of range input (INP), and three bits [bits 2:0] to read back as 0. Set the CRCB bit to 1 for all eight bits [bits 7:0] of the status word to contain 8-bit CRC. See Figure 94 for a visual representation of the two modes.

By default, the optional 8-bit status word is enabled, but can be disabled when operating in SPI interface mode and setting the CS_ENB bit to 1 in the CONFIG register.

Figure 94. Status Word

8.5.5 Cyclic Redundancy Check (CRC)

The ADS127L01 implements two standard CRC algorithms: CRC-4-ITU to provide a 4-bit CRC, and CRC-8-CCITT for an 8-bit CRC. By default, the CRC-4-ITU option is enabled. Set the CRCB bit to 1 in the CONFIG register to change the format to CRC-8-CCITT and remove the system monitor bits from the status word.

The CRC is placed after the ADC data. The CRC is calculated using only the ADC output. When the 4-bit CRC is enabled, the ADS127L01 outputs a 4-bit status block after the CRC that is not used as part of the CRC check.

Table 21. ADS127L01 Register Assignments

8.6.1 ID: ID Control Register (address = 00h) [reset = x3h]

This register is programmed during device manufacture to indicate device characteristics.

8.6.2 CONFIG: ADC Configuration Register (address = 01h) [reset = 00h]

This register contains the software controlled device options.

8.6.3 OFC0: System Offset Calibration Register 0 (address = 02h) [reset = 00h]

This register contains the least significant byte for the system offset calibration. The system offset calibration is a total of three bytes or 24 bits.

8.6.4 OFC1: System Offset Calibration Register 1 (address = 03h) [reset = 00h]

This register contains the middle byte for the system offset calibration. The system offset calibration is a total of three bytes or 24 bits.

8.6.5 OFC2: System Offset Calibration Register 2 (address = 04h) [reset = 00h]

This register contains the most significant byte for the system offset calibration. The system offset calibration is a total of three bytes or 24 bits.

8.6.6 FSC0: System Gain Calibration Register 0 (address = 05h) [reset = 00h]

This register contains the least significant byte for the system gain calibration. The system gain calibration is a total of two bytes or 16 bits.

8.6.7 FSC1: System Gain Calibration Register 1 (address = 06h) [reset = 80h]

This register contains the most significant byte for the system gain calibration. The system gain calibration is a total of two bytes or 16 bits.

8.6.8 MODE: Mode Settings (address = 07h) [reset = xxh]

This register displays the hardware bit settings.