The ADC uses power-supply monitors to detect power-up and supply brownout events. Power-up or power-cycling of the IOVDD digital supply results in device reset. Power-up or power-cycling of the analog power supplies does not reset the ADC.

Figure 8-21 shows the digital power-on thresholds of the IOVDD and the internal CAPD voltages. When the voltages are above their respective thresholds, the ADC is released from reset. DRDY later transitions high when the SPI is ready for communication. If the START pin is high, the ADC immediately begins conversions with the DRDY pin pulsing for each conversion. However, valid conversion data only occur after the power supplies and reference voltage are stabilized. The POR_FLAG bit of the STATUS register indicates the device POR. Write 1b to clear the bit in order to detect the next POR event.

Figure 8-22 shows the power-on thresholds of the analog power supplies. Four monitors are used for four analog supply voltage conditions (AVDD1 – DGND), (AVDD1 – AVSS), (AVDD2 – AVSS), and (CAPA – AVSS). Valid conversion data are available after all power supplies and the reference voltage are stabilized after power-on. The ALV_FLAG bit of the STATUS register sets when any analog power voltage falls below the respective threshold. Write 1b to clear the bit to detect the next analog supply low-voltage condition. Power cycling the analog power supplies does not reset the ADC. Because a low voltage on the IOVDD supply also resets the internal analog LDO (CAPA), the analog low-voltage flag (ALV_FLAG) is also set.