The ADC offers two power-scalable speed modes that determine the range of conversion data rates and power consumed by the ADC. The modes allow optimization of signal bandwidth, data rate, and power consumption. High-speed mode provides maximum data rate and signal bandwidth, and low-speed mode minimizes power consumption for applications that do not require large signal bandwidths. The ADC clock frequency must be adapted to the operating mode. For high-speed mode the clock frequency is 25.6 MHz, and for low-speed mode the clock frequency is 3.2 MHz (see the Section 8.3.3 section for the internal clock divider option). The speed mode is programmed by the SPEED_MODE bit of the CONFIG2 register.