The ADS127L11 is a high performance, 24-bit delta-sigma (ΔΣ) analog-to-digital converter (ADC) offering an excellent combination of dc accuracy and ac precision. The device is optimized to provide high resolution with low power consumption. Integrated input and reference precharge buffers simplify the driver requirements. The digital filter consists of two programmable modes: low-latency mode (typically used for measurement of dc signals) and wideband mode (typically used for measurement of ac signals).

The delta-sigma modulator produces low-resolution, high-frequency data proportional to the signal magnitude. Noise shaping within the modulator shifts the quantization noise of the low-resolution data to an out-of-band frequency range where the noise is removed by the digital filter. The noise remaining within the pass band is white, which is reduced by the digital filter. The digital filter simultaneously decimates and filters the modulator data to provide the high-resolution final output data.

The Section 8.2 shows the features of the ADS127L11. The modulator is a third-order, multibit delta-sigma design that measures the differential input signal, V_IN = (V_AINP – V_AINN), against the differential reference, V_REF = (V_REFP – V_REFN). Input and positive reference precharge buffers reduce the bandwidth and driving requirements of the external input driver. The VCM output provides a buffered mid-supply voltage to drive the common-mode voltage of an external driver stage.

The digital filter offers two modes of operation: the low-latency filter and the wideband filter. The low-latency filter is programmable to sinc4, sinc4 + sinc1, sinc3, and sinc3 + sinc1 modes, allowing optimization between noise performance and latency. The sinc3 + sinc1 filter provides rejection at 400 Hz, 60 Hz, 50 Hz, and 16.6 Hz. The wideband filter is a multi-tap finite impulse response (FIR) design providing outstanding frequency response with low pass-band ripple, steep transition-band, and high stop-band attenuation. Programmable oversampling ratio (OSR) and two speed modes allow optimized choices of bandwidth, resolution, and device power consumption.

The SPI-compatible serial interface is used to configure the device and read conversion data. The interface features daisy-chaining capability for convenient connection of multichannel, simultaneous-sampled systems. Integrated cyclic redundancy check (CRC) error monitoring improves system-level reliability. DRDY is the conversion data-ready output signal.

The device supports external clock operation for ac or dc applications, and internal oscillator operation for dc applications. The START pin synchronizes the digital filter process. The RESET pin resets the ADC.

Supply voltage AVDD1 powers the precharge buffers and the input sampling switches. AVDD2 powers the modulator via an internal regulator (CAPA). Supply voltage IOVDD is the digital I/O voltage that also powers the digital core via an internal regulator (CAPD). The internal regulators minimize overall power consumption and provide consistent levels of performance.