Power-down mode is engaged by setting the PWDN bit of the CONFIG2 register. In power-down mode, the analog and digital sections are powered off, except for a small bias current required to maintain SPI operation needed to exit power-down mode by clearing the register bit. The digital LDO also remains active to maintain user register settings. The sampling of the signal and voltage reference are stopped during power-down mode. Exit power-down mode by writing 0b to the PWDN bit or by resetting the device.