Figure 8-6 shows the block diagram of the internal clock circuit. The ADC can be operated by an external clock or the internal oscillator. The nominal value of f_CLK is 25.6 MHz in high-speed mode and 3.2 MHz in low-speed mode. A divide-by-eight option is available at the CLK input to divide the high-speed mode clock frequency to provide the low-speed mode clock frequency. The clock frequency is divided by two to derive the modulator sampling clock (f_MOD).