In synchronized control mode, the ADC converts continuously regardless if START is high or low. The ADC is synchronized on the rising edge of START. When synchronized, the first DRDY falling edge is delayed to account for the filter settling time (latency time). Both a single-pulse input and a continuous-clock input can be applied to the START pin in this mode.

The ADC synchronizes at the rising edge of START. If the time to the next rising edge of START is an n multiple of the conversion period, within a ±1 / f_CLK window, the ADC does not resynchronize (n = 1, 2, 3, and so on). Synchronization does not occur because the ADC conversion period is already synchronized to the period of the START signal. If the period of the START signal is not an n multiple of the conversion period, the ADC resynchronizes. As a result of the propagation delay of the digital filter, a phase difference exists between the START signal and the DRDY output. Figure 8-25 shows synchronization to the START signal when the period of START pulses is not equal to an n multiple of the conversion period.