The wideband filter is a multistage FIR filter design featuring linear phase response, low pass-band ripple, narrow transition band, and high stop-band attenuation. Because of the superior frequency response characteristics, the filter is well suited for measuring ac signals. The ADC provides eight programmable oversampling ratios (OSR) and two speed modes, offering a range of data rate and resolution to select from.

Figure 8-8 through Figure 8-12 illustrate the frequency response of the wideband filter. Figure 8-8 shows the pass-band ripple. Figure 8-9 shows the detailed frequency response at the transition band.

Figure 8-8 Wideband Filter Pass-Band Ripple

Figure 8-9 Wideband Filter Transition Band

Figure 8-10 shows the frequency response to f_DATA for OSR ≥ 64. The stop band begins at f_DATA / 2 to prevent aliasing at the Nyquist frequency. Figure 8-11 shows the stop-band attenuation to f_MOD for OSR = 32. In the stop-band region, out-of-band input frequencies intermodulate with multiples of the chop frequency at f_MOD / 32, creating a pattern of response peaks that exceed the stop-band attenuation of the digital filter. The width of the response peaks is twice the filter bandwidth. Stop-band attenuation is improved when used in conjunction with an antialias filter at the ADC input. See the Section 9.2 section for details of a fourth-order antialias filter.

OSR ≥ 64

Figure 8-10 Wideband Filter Frequency Response

OSR = 32

Figure 8-11 Wideband Filter Stop-Band Attenuation

Figure 8-12 shows the filter response centered around f_MOD. As shown, the filter response repeats at f_MOD. If not removed by an antialiasing filter, input frequencies at f_MOD appear as aliased frequencies in the pass band. Aliasing also occurs with input frequencies occurring at multiples of f_MOD. These frequency bands are defined by:

where:

• N = 1, 2, 3, and so on
• f_MOD = Modulator sampling frequency
• f_BW = Filter bandwidth

The group delay of the filter is the time for an input signal to propagate from the input to the output of the filter. Because the filter is a linear-phase design, the envelope of a complex input signal is undistorted by the filter. The group delay (expressed in units of time) is constant versus frequency equal to the value = 34 / f_DATA. After a step input is applied, fully settled data occur at 68 data periods later. Figure 8-13 illustrates the filter group delay (34 / f_DATA) and the settling time to a step input (68 / f_DATA).

The digital filter is restarted when the ADC is synchronized. The ADC suppresses the first 68 conversion periods until the filter is fully settled. There is no need to discard data after synchronization. The time of data suppression is the conversion latency time as listed in the latency time column of Table 8-3. A 0.4-μs fixed overhead time is incurred for all data rates. If a step input occurs asynchronous to the conversion period without synchronizing, then the next 69 conversions are partially settled data.