Conversion data are read by taking CS low and by applying SCLK to shift out the data directly (no command is used). Conversion data are buffered, which allows data to be read up to one f_MOD clock cycle before the next DRDY falling edge. Conversion data may be read multiple times until the next conversion data are ready. If the register read command was sent in the previous frame then register data replaces the conversion data.

Figure 8-33 shows an example of reading 24-bit conversion data with the STATUS and CRC bytes disabled.

Figure 8-34 is an example of the long-format read data operation, which includes the STATUS header byte and the CRC byte. This example also shows the optional use of a full-duplex transmission when a register command is input at the same time the conversion data are output. If no input command is desired, the input bytes are 00h, 00h, and D7h. The output CRC (CRC-OUT) code computation includes the STATUS byte. If the conversion data readback is stopped after the eighth SCLK of the MSB data, DRDY returns high and the DRDY bit of the STATUS header goes low to indicate a data-read attempt.

Conversion data can be read asynchronous to DRDY. However, when conversion data are read close to the DRDY falling edge, there is uncertainty whether previous data or new data are output. If the SCLK shift operation starts at least one f_MOD clock cycle before the DRDY falling edge, then old data are provided. If the shift operation starts at least one f_MOD clock cycle after DRDY, then new data are output. The DRDY bit of the STATUS header indicates if the data are old (previously read data) or new.