ZHCSES2H December   2009  – February 2016 ADS1282-HT

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Recommended Operating Conditions
    3. 7.3  Thermal Information
    4. 7.4  Electrical Characteristics
    5. 7.5  Electrical Characteristics (PW Package)
    6. 7.6  Timing Requirements
    7. 7.7  Pulse-Sync Timing Requirements
    8. 7.8  Reset Timing Requirements
    9. 7.9  Switching Characteristics
    10. 7.10 Modulator Switching Characteristics
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Noise Performance
      2. 8.3.2  Input-Referred Noise
      3. 8.3.3  Idle Tones
      4. 8.3.4  Operating Mode
      5. 8.3.5  Analog Inputs and Multiplexer
      6. 8.3.6  PGA (Programmable Gain Amplifier)
      7. 8.3.7  ADC
      8. 8.3.8  Modulator
      9. 8.3.9  Modulator Over-Range
      10. 8.3.10 Modulator Input Impedance
      11. 8.3.11 Modulator Over-Range Detection (MFLAG)
      12. 8.3.12 Voltage Reference Inputs (VREFP, VREFN)
      13. 8.3.13 Digital Filter
        1. 8.3.13.1 Sinc Filter Stage (Sinx/X)
        2. 8.3.13.2 FIR Stage
        3. 8.3.13.3 Group Delay and Step Response
          1. 8.3.13.3.1 Linear Phase Response
          2. 8.3.13.3.2 Minimum Phase Response
        4. 8.3.13.4 HPF Stage
      14. 8.3.14 Master Clock Input (CLK)
      15. 8.3.15 Synchronization (SYNC Pin and Sync Command)
      16. 8.3.16 Pulse-Sync Mode
      17. 8.3.17 Continuous-Sync Mode
      18. 8.3.18 Reset (RESET Pin and Reset Command)
      19. 8.3.19 Power-Down (PWDN Pin and Standby Command)
      20. 8.3.20 Power-On Sequence
      21. 8.3.21 Serial Interface
        1. 8.3.21.1 Serial Clock (SCLK)
        2. 8.3.21.2 Data Input (DIN)
        3. 8.3.21.3 Data Output (DOUT)
        4. 8.3.21.4 Data Ready (DRDY)
      22. 8.3.22 Data Format
      23. 8.3.23 Reading Data
        1. 8.3.23.1 Read Data Continuous
        2. 8.3.23.2 Read Data by Command
      24. 8.3.24 One-Shot Operation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Modulator Output Mode
    5. 8.5 Programming
      1. 8.5.1 Commands
        1. 8.5.1.1  WAKEUP: Wake-Up from Standby Mode
        2. 8.5.1.2  STANDBY: Standby Mode
        3. 8.5.1.3  SYNC: Synchronize the A/D Conversion
        4. 8.5.1.4  RESET: Reset the Device
        5. 8.5.1.5  RDATAC: Read Data Continuous
        6. 8.5.1.6  SDATAC: Stop Read Data Continuous
        7. 8.5.1.7  RDATA: Read Data By Command
        8. 8.5.1.8  RREG: Read Register Data
        9. 8.5.1.9  WREG: Write to Register
        10. 8.5.1.10 OFSCAL: Offset Calibration
        11. 8.5.1.11 GANCAL: Gain Calibration
      2. 8.5.2 Calibration Commands
        1. 8.5.2.1 OFSCAL Command
        2. 8.5.2.2 GANCAL Command
      3. 8.5.3 User Calibration
      4. 8.5.4 Configuration Guide
    6. 8.6 Register Maps
      1. 8.6.1 ADS1282-HT Register Map Information
      2. 8.6.2 ID Register
      3. 8.6.3 Configuration Registers
        1. 8.6.3.1 Configuration Register 0
        2. 8.6.3.2 Configuration Register 1
      4. 8.6.4 HPF1 and HPF0
        1. 8.6.4.1 High-Pass Filter Corner Frequency, Low Byte
        2. 8.6.4.2 High-Pass Filter Corner Frequency, High Byte
      5. 8.6.5 OFC2, OFC1, OFC0
        1. 8.6.5.1 Offset Calibration, Low Byte
        2. 8.6.5.2 Offset Calibration, Mid Byte
        3. 8.6.5.3 Offset Calibration, High Byte
      6. 8.6.6 FSC2, FSC1, FSC0
        1. 8.6.6.1 Full-Scale Calibration, Low Byte
        2. 8.6.6.2 Full-Scale Calibration, Mid Byte
        3. 8.6.6.3 Full-Scale Calibration, High Byte
      7. 8.6.7 Offset and Full-Scale Calibration Registers
        1. 8.6.7.1 OFC[2:0] Registers
        2. 8.6.7.2 FSC[2:0] Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Geophone Interface Typical Application
        1. 9.2.1.1 Detailed Design Procedure
      2. 9.2.2 Digital Connection to a Field Programmable Gate Array (FPGA) Device Typical Application
        1. 9.2.2.1 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 HPF 传递函数
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

JDJ or PW Package
28-Pin CDIP SB or TSSOP
Top View
ADS1282-HT jd_pw_po_bas446.gif

Pin Functions

PIN I/O DESCRIPTION
NAME CDIP SB TSSOP
CLK 1 1 Digital input Master clock input
SCLK 2 2 Digital input Serial clock input
DRDY 3 3 Digital output Data ready output: read data on falling edge
DOUT 4 4 Digital output Serial data output
DIN 5 5 Digital input Serial data input
MCLK 7 7 Digital I/O Modulator clock output; if in modulator mode:
MCLK: Modulator clock output
Otherwise, the pin is an unused input (must be tied).
M1 8 8 Digital I/O Modulator data output 1; if in modulator mode:
M1: Modulator data output 1
Otherwise, the pin is an unused input (must be tied).
M0 9 9 Digital I/O Modulator data output 0; if in modulator mode:
M0: Modulator data output 0
Otherwise, the pin is an unused input (must be tied).
SYNC 10 10 Digital input Synchronize input
MFLAG 11 11 Digital output Modulator Over-Range flag: 0 = normal, 1 = modulator over-range
DGND 6 6 Digital ground Digital ground, pin 12 is the key ground point
12 12
27 25
29 27
CAPN 13 13 Analog PGA outputs: Connect 10-nF capacitor from CAPP to CAPN
CAPP 14 14 Analog PGA outputs: Connect 10-nF capacitor from CAPP to CAPN
AINP2 15 15 Analog input Positive analog input 2
AINN2 16 16 Analog input Negative analog input 2
AINP1 17 17 Analog input Positive analog input 1
AINN1 18 18 Analog input Negative analog input 1
AVDD 19 19 Analog supply Positive analog power supply
20
AVSS 21 20 Analog supply Negative analog power supply
22
VREFN 23 21 Analog input Negative reference input
VREFP 24 22 Analog input Positive reference input
PWDN 25 23 Digital input Power-down input, active low
RESET 26 24 Digital input Reset input, active low
DVDD 28 26 Digital supply Digital power supply: 1.8 V to 3.3 V
BYPAS 30 28 Analog Sub-regulator output: Connect 1-μF capacitor to DGND
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