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7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
AVDD to AVSS	–0.3	5.5	V
AVSS to DGND	–2.8	0.3	V
DVDD to DGND	–0.3	3.9	V
Input current		100, momentary	mA
Input current		10, continuous	mA
Analog input voltage (AINP1, AINN1, AINP2, AINN2, VREFN, VREFP, CAPP, CAPN)	AVSS – 0.3	AVDD + 0.3	V
Digital input voltage to DGND (CLK, SCLK, DRDY, DOUT, DIN, MCLK, M1, M0, MFLAG, SYNC, PWDN, RESET)	–0.3	DVDD + 0.3	V
Storage temperature, T_stg	–60	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
Operating temperature		–55		125	°C

7.3 Thermal Information

THERMAL METRIC⁽¹⁾		ADS1282-HT		UNIT
		JDJ (CDIP SB)	PW (TSSOP)
		28 PINS	28 PINS
R_θJA	Junction-to-ambient thermal resistance	43.1	54.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	14.03	11.3	°C/W
R_θJB	Junction-to-board thermal resistance	23.2	13	°C/W
ψ_JT	Junction-to-top characterization parameter	N/A	0.5	°C/W
ψ_JB	Junction-to-board characterization parameter	N/A	12.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	4.98	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.4 Electrical Characteristics

Limit specifications at –55°C to 210°C. Typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒ_CLK⁽¹⁾ = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10 nF, PGA = 1, and ƒ_DATA = 1000 SPS, unless otherwise noted.

PARAMETER		TEST CONDITIONS	T_A = –55°C to 125°C			T_A = 210°C⁽²⁾			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	MIN	TYP	MAX	UNIT
ANALOG INPUTS
Full-scale input voltage		V_IN = (AINP – AINN)		±V_REF/(2 × PGA)					V
Absolute input range	AINP or AINN		AVSS + 0.7		AVDD – 1.25	AVSS + 0.7		AVDD – 1.25	V
PGA input voltage noise density				5					nV/√Hz
Differential input impedance⁽³⁾				1					GΩ
Common-mode input impedance				100					MΩ
Input bias current				1			1000		nA
Crosstalk		ƒ = 31.25 Hz		–128			–123		dB
MUX ON-resistance				30			45		Ω
PGA OUTPUT (CAPP, CAPN)
Absolute output range			AVSS + 0.4		AVDD – 0.4	AVSS + 0.4		AVDD – 0.4	V
PGA differential output impedance				600			600		Ω
Output impedance tolerance				±10%			±10%
External bypass capacitance				10	100		10		nF
Modulator differential input impedance				55					kΩ
AC PERFORMANCE
Signal-to-noise ratio⁽⁴⁾	SNR		112	124		110	122		dB
Total harmonic distortion⁽⁵⁾	THD	PGA = 1...16		–122	–99		–102	–99	dB
		PGA = 32		–117	–99		–98	–94
		PGA = 64		–115			–93
Spurious-free dynamic range	SFDR			123					dB
DC PERFORMANCE
Resolution		No missing codes	31			31			bits
Data rate	ƒ_DATA	FIR filter mode	250		4000	250		4000	SPS
Data rate	ƒ_DATA	Sinc filter mode	8000		128000	8000		128000	SPS
Integral nonlinearity (INL)⁽⁶⁾		Differential input		0.00005	0.0090		0.002	0.01	% FSR⁽⁷⁾
Offset error		Shorted input		50	200		99	250	μV
Offset error after calibration⁽⁸⁾				1			2		μV
Offset drift				0.02			0.19		μV/°C
Gain error⁽⁹⁾			–1.5%	–1%	–0.5%	–1.5%	–1%	–0.5%
Gain error after calibration⁽⁸⁾				0.0002%			0.0002%
Gain drift		PGA = 1		2			3		ppm/°C
Gain drift		PGA = 16		9			11		ppm/°C
Gain matching⁽¹³⁾				0.3%	0.8%			0.8%
Common-mode rejection		ƒ_CM = 60 Hz⁽¹⁰⁾	82	110		82	137		dB
Power-supply rejection	AVDD, AVSS	ƒ_PS = 60 Hz⁽¹⁰⁾	80	90			83		dB
Power-supply rejection	DVDD	ƒ_PS = 60 Hz⁽¹⁰⁾	90	115			101		dB
VOLTAGE REFERENCE INPUTS
Reference input voltage		(V_REF = VREFP – VREFN)	0.5	5	(AVDD – AVSS) + 0.2	0.5		(AVDD – AVSS) + 0.2	V
Negative reference input	VREFN		AVSS – 0.1		VREFP – 0.5	AVSS – 0.1		VREFP – 0.5	V
Positive reference input	VREFP		VREFN + 0.5		AVDD + 0.1	VREFN + 0.5		AVDD + 0.1	V
Reference input impedance				85			85		kΩ
DIGITAL FILTER RESPONSE
Passband ripple					±0.003				dB
Passband (–0.01 dB)				0.375 × ƒ_DATA					Hz
Bandwidth (–3 dB)				0.413 × ƒ_DATA					Hz
High-pass filter corner			0.1		10				Hz
Stop band attenuation⁽¹¹⁾			135						dB
Stop band				0.500 × ƒ_DATA					Hz
Group delay		Minimum phase filter		5 / ƒ_DATA					s
		Linear phase filter		31 / ƒ_DATA
Settling time (latency)		Minimum phase filter		62 / ƒ_DATA					s
Settling time (latency)		Linear phase filter		62 / ƒ_DATA					s
DIGITAL INPUT/OUTPUT
V_IH			0.8 × DVDD		DVDD	0.8 × DVDD		DVDD	V
V_IL			DGND		0.2 × DVDD	DGND		0.2 × DVDD	V
V_OH		I_OH = 1 mA	0.8 × DVDD			0.8 × DVDD			V
V_OL		I_OL = 1 mA			0.2 × DVDD			0.2 × DVDD	V
Input leakage		0 < V_{DIGITAL IN} < DVDD			±10			±10	μA
POWER SUPPLY
AVSS			–2.6		0	–2.6		0	V
AVDD			AVSS + 4.75		AVSS + 5.25	AVSS + 4.75		AVSS + 5.25	V
DVDD			1.75		3.6	1.75		3.6	V
AVDD, AVSS current		High-resolution mode		4.5	7.2		5.2	10	\|mA\|
		Standby mode		68	250		3000	3700	\|μA\|
		Power-down mode		68	250		3000	3700	\|μA\|
DVDD current		All modes		0.6	1.5		1.2	2	mA
		Modulator mode		0.1			1.1		mA
		Standby mode		73	175		576	950	μA
		Power-down mode⁽¹²⁾		32	120		186	240	μA
Power dissipation		High-resolution mode		25	41		29.7	56.1	mW
		Standby mode		0.58	1.1		16.9	21.6	mW
		Power-down mode		0.45	0.95		15.6	19.3	mW

(1) ƒ_CLK = system clock.

(2) Minimum and maximum parameters are characterized for operation at T_A = 210°C, but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.

(3) Input impedance is improved by disabling input chopping (CHOP bit = 0).

(4) V_IN = 20mV_DC/PGA, see Table 1.

(5) V_IN = 31.25 Hz, –0.5 dBFS.

(6) Best-fit method.

(7) FSR: Full-scale range = ±V_REF / (2 × PGA).

(8) Calibration accuracy is on the level of noise reduced by 4 (calibration averages 16 readings).

(9) The PGA output impedance and the modulator input impedance results in –1% systematic gain error.

(10) ƒ_CM is the input common-mode frequency. ƒ_PS is the power-supply frequency.

(11) Input frequencies in the range of Nƒ_CLK / 512 ± ƒ_DATA / 2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency ranges intermodulation = 120 dB, typ.

(12) CLK input stopped.

(13) Gain match relative to PGA = 1.

7.5 Electrical Characteristics (PW Package)

Limit specifications at –55°C to 175°C. Typical specifications at 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒ_CLK⁽¹⁾ = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10 nF, PGA = 1, and ƒ_DATA = 1000 SPS, unless otherwise noted.

PARAMETER		TEST CONDITIONS	T_A = –55°C to 125°C			T_A = 175°C⁽²⁾			UNIT
PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	MIN	TYP	MAX	UNIT
ANALOG INPUTS
Full-scale input voltage		V_IN = (AINP – AINN)		±V_REF / (2 × PGA)			±V_REF / (2 × PGA)		V
Absolute input range	AINP or AINN		AVSS + 0.7		AVDD – 1.25	AVSS + 0.7		AVDD – 1.25	V
PGA input voltage noise density				5			5		nV/√Hz
Differential input impedance⁽³⁾				1			1		GΩ
Common-mode input impedance				100			100		MΩ
Input bias current				1			1000		nA
Crosstalk		f = 31.25 Hz		–128			–123		dB
MUX on-resistance				30			45		Ω
PGA OUTPUT (CAPP, CAPN)
Absolute output range			AVSS + 0.4		AVDD – 0.4	AVSS + 0.4		AVDD – 0.4	V
PGA differential output impedance				600			600		Ω
Output impedance tolerance				±10%			±10%
External bypass capacitance				10	100		10		nF
Modulator differential input impedance				55			55		kΩ
AC PERFORMANCE
Signal-to-noise ratio⁽⁴⁾	SNR		112	124		112	122		dB
Total harmonic distortion⁽⁵⁾	THD	PGA = 1...16		–122	–99		–112	–99	dB
		PGA = 32		–117	–99		–106	–94
		PGA = 64		–115			–102
Spurious-free dynamic range	SFDR			123					dB
DC PERFORMANCE
Resolution		No missing codes	31			31			bits
Data rate	ƒ_DATA	FIR filter mode	250		4000	250		4000	SPS
Data rate	ƒ_DATA	Sinc filter mode	8000		128000	8000		128000	SPS
Integral nonlinearity (INL)⁽⁶⁾		Differential input		0.00005	0.009		0.00004	0.009	% FSR⁽⁷⁾
Offset error		Shorted input		50	200		50	200	μV
Offset error after calibration⁽⁸⁾				1			2		μV
Offset drift				0.02			0.19		μV/°C
Gain error⁽⁹⁾			–1.5%	–1%	–0.5%	–1.5%	–1%	–0.5%
Gain error after calibration⁽⁸⁾				0.0002%			0.0002%
Gain drift		PGA = 1		2			2		ppm/°C
Gain drift		PGA = 16		9			11		ppm/°C
Gain matching⁽¹³⁾				0.3%	0.8%		0.4%	0.8%
Common-mode rejection		ƒ_CM = 60 Hz⁽¹⁰⁾	82	110		82	114		dB
Power-supply rejection	AVDD, AVSS	ƒ_PS = 60 Hz⁽¹⁰⁾	80	90			84		dB
Power-supply rejection	DVDD	ƒ_PS = 60 Hz⁽¹⁰⁾	90	115			106		dB
VOLTAGE REFERENCE INPUTS
Reference input voltage		(V_REF = VREFP – VREFN)	0.5	5	(AVDD – AVSS) + 0.2	0.5		(AVDD – AVSS) + 0.2	V
Negative reference input	VREFN		AVSS – 0.1		VREFP – 0.5	AVSS – 0.1		VREFP – 0.5	V
Positive reference input	VREFP		VREFN + 0.5		AVDD + 0.1	VREFN + 0.5		AVDD + 0.1	V
Reference input impedance				85			85		kΩ
DIGITAL FILTER RESPONSE
Passband ripple					±0.003			±0.003	dB
Passband (–0.01 dB)				0.375 × ƒ_DATA			0.375 × ƒ_DATA		Hz
Bandwidth (–3 dB)				0.413 × ƒ_DATA			0.413 × ƒ_DATA		Hz
High-pass filter corner			0.1		10	0.1		10	Hz
Stop band attenuation⁽¹¹⁾			135			135			dB
Stop band				0.500 × ƒ_DATA			0.500 × ƒ_DATA		Hz
DIGITAL INPUT/OUTPUT
V_IH			0.8 × DVDD		DVDD	0.8 × DVDD		DVDD	V
V_IL			DGND		0.2 × DVDD	DGND		0.2 × DVDD	V
V_OH		I_OH = 1 mA	0.8 × DVDD			0.8 × DVDD			V
V_OL		I_OL = 1 mA			0.2 × DVDD			0.2 × DVDD	V
Input leakage		0 < V_{DIGITAL IN} < DVDD			±10			±10	μA
POWER SUPPLY
AVSS			–2.6		0	–2.6		0	V
AVDD			AVSS + 4.75		AVSS + 5.25	AVSS + 4.75		AVSS + 5.25	V
DVDD			1.75		3.6	1.75		3.6	V
AVDD, AVSS current		High-resolution mode		4.5	7.2		5.2	9.2	\|mA\|
		Standby mode		68	110		52	900	\|μA\|
		Power-down mode		68	110		52	900	\|μA\|
DVDD current		All modes		0.6	1.5		0.7	1.5	mA
		Modulator mode		0.1			1.05		mA
		Standby mode		73	175		255	600	μA
		Power-down mode⁽¹²⁾		32	120		118	220	μA
Power dissipation		High-resolution mode		25	41		31	41	mW
		Standby mode		0.58	1.1		2.5	5	mW
		Power-down mode		0.45	0.95		2.06	4.5	mW

(1) ƒ_CLK = System clock

(2) Minimum and maximum parameters are characterized for operation at T_A = 175°C, but may not be production tested at that temperature. Production test limits with statistical guardbands are used to ensure high temperature performance.

(3) Input impedance is improved by disabling input chopping (CHOP bit = 0).

(4) V_IN = 20 mV_DC / PGA, see Table 1.

(5) V_IN = 31.25 Hz, –0.5 dBFS.

(6) Best-fit method.

(7) FSR: Full-scale range = ±V_REF / (2 × PGA).

(8) Calibration accuracy is on the level of noise reduced by 4 (calibration averages 16 readings).

(9) The PGA output impedance and the modulator input impedance results in –1% systematic gain error.

(10) ƒ_CM is the input common-mode frequency. ƒ_PS is the power-supply frequency.

(11) Input frequencies in the range of Nƒ_CLK / 512 ± ƒ_DATA / 2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency ranges intermodulation = 120 dB, typ.

(12) CLK input stopped.

(13) Gain match relative to PGA = 1.

7.6 Timing Requirements

At T_A = –55°C to 210°C and DVDD = 1.65 to 3.6 V, unless otherwise noted.

		T_A = –55°C to 125°C		T_A = 175°C		T_A = 210°C		UNIT
		MIN	MAX	MIN	MAX	MIN	MAX	UNIT
t_SCLK	SCLK period	2	16	2	16	2	16	1 / ƒ_CLK
t_{SPWH, L}	SCLK pulse width, high and low⁽¹⁾	0.8	10	0.8	10	0.8	10	1 / ƒ_CLK
t_DIST	DIN valid to SCLK rising edge: setup time	50		50		50		ns
t_DIHD	Valid DIN to SCLK rising edge: hold time	50		50		50		ns
t_DOPD	SCLK falling edge to valid new DOUT: propagation delay⁽²⁾		100		100		100	ns
t_DOHD	SCLK falling edge to DOUT invalid: hold time	0		0		0		ns
t_SCDL	Final SCLK rising edge of command to first SCLK rising edge for register read/write data	24		24		24		1 / ƒ_CLK
DIGITAL INPUT/OUTPUT
Clock input	ƒ_CLK	1	4.096			1	4.096	MHz
Serial clock rate	ƒ_SCLK		ƒ_CLK/2				ƒ_CLK/2	MHz

(1) Holding SCLK low for 64 DRDY falling edges resets the serial interface.

(2) Load on DOUT = 20 pF || 100 kΩ.

7.7 Pulse-Sync Timing Requirements

See Figure 46 and Figure 47 for timing diagrams.

		MIN	MAX	UNIT
t_SYNC	SYNC period⁽¹⁾	1	Infinite	n / ƒ_DATA
t_CSHD	CLK to SYNC hold time to not latch on CLK edge	10		ns
t_SCSU	SYNC to CLK setup time to latch on CLK edge	10		ns
t_{SPWH, L}	SYNC pulse width, high or low	2		1 / ƒ_CLK
t_DR	Time for data ready (SINC filter)	See 器件支持, Table 20
t_DR	Time for data ready (FIR filter)	62.98046875 / ƒ_DATA + 466 / ƒ_CLK

(1) Continuous-Sync mode; a free-running SYNC clock input without causing re-synchronization.

7.8 Reset Timing Requirements

See Figure 48 for timing diagram.

		MIN	UNIT
t_CRHD	CLK to RESET hold time	10	ns
t_RCSU	RESET to CLK setup time	10	ns
t_RST	RESET low	2	1 / ƒ_CLK
t_DR	Time for data ready	62.98046875 / ƒ_DATA + 468 / ƒ_CLK	s

Read Data Timing Requirements

		MIN	MAX	UNIT
t_DDPD	DRDY to valid MSB on DOUT propagation delay (see Figure 54)⁽¹⁾		100	ns
t_DR	Time for new data after data read command (see Figure 55)	0	1	ƒ_DATA

(1) Load on DOUT = 20 pF || 100 kΩ.

7.9 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER	TEST CONDITIONS	TYP	UNIT
Group delay⁽¹⁾	Minimum phase filter	5 / ƒ_DATA	s
Group delay⁽¹⁾	Linear phase filter	31 / ƒ_DATA	s
Settling time (latency)	Minimum phase filter	62 / ƒ_DATA	s
Settling time (latency)	Linear phase filter	62 / ƒ_DATA	s

(1) At DC. See Figure 42.

7.10 Modulator Switching Characteristics

See Figure 56.

PARAMETER		MIN	TYP	MAX	UNIT
t_MCD0, 1	MCLK rising edge to M0, M1 valid propagation delay⁽¹⁾			100	ns
t_CMD	CLK rising edge (after SYNC rising edge) to MCLK rising edge CMD		5		1/ƒ_CLK
t_CSHD	CLK to SYNC hold time to not latch on CLK edge	10			ns
t_SCSU	SYNC to CLK setup time to latch on CLK edge	10			ns
t_SYMD	SYNC to stable bit stream			16	1/ƒ_MOD

(1) Load on M0 and M1 = 20 pF || 100 kΩ.

7.11 Typical Characteristics

At 25°C, AVDD = 2.5 V, AVSS = –2.5 V, ƒ_CLK = 4.096 MHz, VREFP = 2.5 V, VREFN = –2.5 V, DVDD = 3.3 V, CAPN – CAPP = 10 nF, PGA = 1, and ƒ_DATA = 1000 SPS, unless otherwise noted.