9.2.2.1 Design Requirements

It is critical to match the DVDD input and output thresholds of the ADS1282 to the IO voltage of the FPGA. The FPGA outputs with correct VOH and VOL levels must be compatible with VIH/VIL levels of ADS1282 utilizing respective DVDD voltage. Conversely the FPGA input thresholds must also be compatible with VOH/VOL levels of DVDD range of ADS1282. The wide DVDD range of the ADS1282 allows easy interfacing to 1.8-V, 2.5-V, and 3.3-V logic levels. If DVDD is less than 2.25, then the BYPAS pin must be directly connected to DVDD to BYPAS internal LDO.