9.2.2.2 Detailed Design Procedure

The modulator over-range flag (MFLAG) from each device ties to the FPGA. For synchronization, one SYNC control line connects all ADS1282-SP devices. The RESET line also connects to all ADS1282-SP devices.

For best performance, the FPGA and the ADS1282-SPs should operate from the same clock. Avoid ringing on the digital inputs. 47-Ω resistors in series with the digital traces can help to reduce ringing by controlling impedances. Place the resistors at the source (driver) end of the trace. Unused digital inputs should not float; use pullups or pulldowns to DVDD or GND. This includes the modulator data pins, M0, M1, and MCLK.

Placement and layout of multiple ADS1282s should be done to allow digital and analog signals to be separated and not cross to minimize coupling of noise from digital signals to analog signals and prevent ground loops. FPGA firmware can monitor DRDY to initiate SPI transactions to obtain samples from both ADS1282s. Additional monitoring of MFLAG can be done to take appropriate action if signal is overrange.